chipdev

chipdev.io Solutions (0x6A73)
git clone https://git.pngu.org/chipdev
Log | Files | Refs | README

Makefile (199B)


1
2
3
4
5
6
7
8
SIM = verilator
TOPLEVEL_LANG = verilog
VERILOG_SOURCES = $(PWD)/router.v
COCOTB_TOPLEVEL = model
COCOTB_TEST_MODULES = router_test
WAVES = 1

include $(shell cocotb-config --makefiles)/Makefile.sim