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authorWilliam Chang <[email protected]>2019-07-13 10:18:33 -0700
committerWilliam Chang <[email protected]>2019-07-13 10:18:33 -0700
commit71493b2f9bbd5f3d18373c518fa14ccafcbf48fc (patch)
tree3bb3e5e496621535611e087720aa5c4d7a533e5e /drivers/arm/i2c_master.h
parent86ad4988fe7ff64916127509d84f44c56fa097aa (diff)
parentda1f05fbc19477c05c0c01bb07fabfaf1ece9d54 (diff)
downloadqmk_firmware-71493b2f9bbd5f3d18373c518fa14ccafcbf48fc.tar.gz
qmk_firmware-71493b2f9bbd5f3d18373c518fa14ccafcbf48fc.zip
Merge branch 'master' of https://github.com/qmk/qmk_firmware
Diffstat (limited to 'drivers/arm/i2c_master.h')
-rw-r--r--drivers/arm/i2c_master.h40
1 files changed, 38 insertions, 2 deletions
diff --git a/drivers/arm/i2c_master.h b/drivers/arm/i2c_master.h
index a15f1702dd..1bb74c800f 100644
--- a/drivers/arm/i2c_master.h
+++ b/drivers/arm/i2c_master.h
@@ -26,9 +26,19 @@
#include "ch.h"
#include <hal.h>
-#ifndef I2C1_BANK
- #define I2C1_BANK GPIOB
+#ifdef I2C1_BANK
+ #define I2C1_SCL_BANK I2C1_BANK
+ #define I2C1_SDA_BANK I2C1_BANK
#endif
+
+#ifndef I2C1_SCL_BANK
+ #define I2C1_SCL_BANK GPIOB
+#endif
+
+#ifndef I2C1_SDA_BANK
+ #define I2C1_SDA_BANK GPIOB
+#endif
+
#ifndef I2C1_SCL
#define I2C1_SCL 6
#endif
@@ -36,6 +46,32 @@
#define I2C1_SDA 7
#endif
+// The default PAL alternate modes are used to signal that the pins are used for I2C
+#ifndef I2C1_SCL_PAL_MODE
+ #define I2C1_SCL_PAL_MODE 4
+#endif
+#ifndef I2C1_SDA_PAL_MODE
+ #define I2C1_SDA_PAL_MODE 4
+#endif
+
+// The default timing values below configures the I2C clock to 400khz assuming a 72Mhz clock
+// For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html
+#ifndef I2C1_TIMINGR_PRESC
+ #define I2C1_TIMINGR_PRESC 15U
+#endif
+#ifndef I2C1_TIMINGR_SCLDEL
+ #define I2C1_TIMINGR_SCLDEL 4U
+#endif
+#ifndef I2C1_TIMINGR_SDADEL
+ #define I2C1_TIMINGR_SDADEL 2U
+#endif
+#ifndef I2C1_TIMINGR_SCLH
+ #define I2C1_TIMINGR_SCLH 15U
+#endif
+#ifndef I2C1_TIMINGR_SCLL
+ #define I2C1_TIMINGR_SCLL 21U
+#endif
+
#ifndef I2C_DRIVER
#define I2C_DRIVER I2CD1
#endif