diff options
Diffstat (limited to 'platforms')
40 files changed, 8154 insertions, 0 deletions
| diff --git a/platforms/chibios/BLACKPILL_STM32_F401/board/board.mk b/platforms/chibios/BLACKPILL_STM32_F401/board/board.mk new file mode 100644 index 0000000000..fddf7dace4 --- /dev/null +++ b/platforms/chibios/BLACKPILL_STM32_F401/board/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F401C_DISCOVERY/board.c + +# Required include directories +BOARDINC = $(CHIBIOS)/os/hal/boards/ST_STM32F401C_DISCOVERY + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC  += $(BOARDINC) diff --git a/platforms/chibios/BLACKPILL_STM32_F401/configs/board.h b/platforms/chibios/BLACKPILL_STM32_F401/configs/board.h new file mode 100644 index 0000000000..30af6b0c86 --- /dev/null +++ b/platforms/chibios/BLACKPILL_STM32_F401/configs/board.h @@ -0,0 +1,20 @@ +/* Copyright 2020 Nick Brassel (tzarc) + * + *  This program is free software: you can redistribute it and/or modify + *  it under the terms of the GNU General Public License as published by + *  the Free Software Foundation, either version 3 of the License, or + *  (at your option) any later version. + * + *  This program is distributed in the hope that it will be useful, + *  but WITHOUT ANY WARRANTY; without even the implied warranty of + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the + *  GNU General Public License for more details. + * + *  You should have received a copy of the GNU General Public License + *  along with this program.  If not, see <https://www.gnu.org/licenses/>. + */ +#pragma once + +#include_next "board.h" + +#undef STM32_HSE_BYPASS diff --git a/platforms/chibios/BLACKPILL_STM32_F401/configs/chconf.h b/platforms/chibios/BLACKPILL_STM32_F401/configs/chconf.h new file mode 100644 index 0000000000..7dc4f84a8a --- /dev/null +++ b/platforms/chibios/BLACKPILL_STM32_F401/configs/chconf.h @@ -0,0 +1,714 @@ +/* +    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + +    Licensed under the Apache License, Version 2.0 (the "License"); +    you may not use this file except in compliance with the License. +    You may obtain a copy of the License at + +        http://www.apache.org/licenses/LICENSE-2.0 + +    Unless required by applicable law or agreed to in writing, software +    distributed under the License is distributed on an "AS IS" BASIS, +    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +    See the License for the specific language governing permissions and +    limitations under the License. +*/ + +/** + * @file    rt/templates/chconf.h + * @brief   Configuration file template. + * @details A copy of this file must be placed in each project directory, it + *          contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_6_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief   System time counter resolution. + * @note    Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION                32 +#endif + +/** + * @brief   System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + *          setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY                 10000 +#endif + +/** + * @brief   Time intervals data size. + * @note    Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE               32 +#endif + +/** + * @brief   Time types data size. + * @note    Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE              32 +#endif + +/** + * @brief   Time delta constant for the tick-less mode. + * @note    If this value is zero then the system uses the classic + *          periodic tick. This value represents the minimum number + *          of ticks that is safe to specify in a timeout directive. + *          The value one is not valid, timeouts are rounded up to + *          this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA                 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief   Round robin interval. + * @details This constant is the number of system ticks allowed for the + *          threads before preemption occurs. Setting this value to zero + *          disables the preemption for threads with equal priority and the + *          round robin becomes cooperative. Note that higher priority + *          threads can still preempt, the kernel is always preemptive. + * @note    Disabling the round robin preemption makes the kernel more compact + *          and generally faster. + * @note    The round robin preemption is not supported in tickless mode and + *          must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM                 0 +#endif + +/** + * @brief   Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + *          then the whole available RAM is used. The core memory is made + *          available to the heap allocator and/or can be used directly through + *          the simplified core memory allocator. + * + * @note    In order to let the OS manage the whole RAM the linker script must + *          provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note    Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE                 0 +#endif + +/** + * @brief   Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + *          does not spawn the idle thread. The application @p main() + *          function becomes the idle thread and must implement an + *          infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD               FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief   OS optimization. + * @details If enabled then time efficient rather than space efficient code + *          is used when two possible implementations exist. + * + * @note    This is not related to the compiler optimization options. + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED               TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief   Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + *          the kernel. + * + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM                       TRUE +#endif + +/** + * @brief   Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY                 TRUE +#endif + +/** + * @brief   Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + *          the kernel. + * + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT                 TRUE +#endif + +/** + * @brief   Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES               TRUE +#endif + +/** + * @brief   Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + *          priority rather than in FIFO order. + * + * @note    The default is @p FALSE. Enable this if you have special + *          requirements. + * @note    Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY      FALSE +#endif + +/** + * @brief   Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES                  TRUE +#endif + +/** + * @brief   Enables recursive behavior on mutexes. + * @note    Recursive mutexes are heavier and have an increased + *          memory footprint. + * + * @note    The default is @p FALSE. + * @note    Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE        FALSE +#endif + +/** + * @brief   Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + *          in the kernel. + * + * @note    The default is @p TRUE. + * @note    Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS                 TRUE +#endif + +/** + * @brief   Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + *          specification are included in the kernel. + * + * @note    The default is @p TRUE. + * @note    Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT         TRUE +#endif + +/** + * @brief   Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS                   TRUE +#endif + +/** + * @brief   Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + *          are included in the kernel. + * + * @note    The default is @p TRUE. + * @note    Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT           TRUE +#endif + +/** + * @brief   Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + *          in the kernel. + * + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES                 TRUE +#endif + +/** + * @brief   Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + *          FIFO order. + * + * @note    The default is @p FALSE. Enable this if you have special + *          requirements. + * @note    Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY        FALSE +#endif + +/** + * @brief   Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + *          included in the kernel. + * + * @note    The default is @p TRUE. + * @note    Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES                TRUE +#endif + +/** + * @brief   Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + *          in the kernel. + * + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE                  TRUE +#endif + +/** + * @brief   Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + *          in the kernel. + * + * @note    The default is @p TRUE. + * @note    Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + *          @p CH_CFG_USE_SEMAPHORES. + * @note    Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP                     TRUE +#endif + +/** + * @brief   Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + *          in the kernel. + * + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS                 TRUE +#endif + +/** + * @brief   Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + *          in the kernel. + * + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS                TRUE +#endif + +/** + * @brief   Pipes APIs. + * @details If enabled then the pipes APIs are included + *          in the kernel. + * + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES                    TRUE +#endif + +/** + * @brief   Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + *          in the kernel. + * + * @note    The default is @p TRUE. + * @note    Requires @p CH_CFG_USE_WAITEXIT. + * @note    Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC                  TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief   Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + *          kernel. + * + * @note    The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY                  TRUE +#endif + +/** + * @brief   Maximum length for object names. + * @details If the specified length is zero then the name is stored by + *          pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH     8 +#endif + +/** + * @brief   Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY     TRUE +#endif + +/** + * @brief   Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS      TRUE +#endif + +/** + * @brief   Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES           TRUE +#endif + +/** + * @brief   Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES            TRUE +#endif + +/** + * @brief   Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS            TRUE +#endif + +/** + * @brief   Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES                TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief   Debug option, kernel statistics. + * + * @note    The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS                   FALSE +#endif + +/** + * @brief   Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + *          at runtime. + * + * @note    The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK           FALSE +#endif + +/** + * @brief   Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + *          parameters are activated. + * + * @note    The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS                FALSE +#endif + +/** + * @brief   Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + *          activated. This includes consistency checks inside the kernel, + *          runtime anomalies and port-defined checks. + * + * @note    The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS               FALSE +#endif + +/** + * @brief   Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note    The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK                   CH_DBG_TRACE_MASK_DISABLED +#endif + +/** + * @brief   Trace buffer entries. + * @note    The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + *          different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE            128 +#endif + +/** + * @brief   Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note    The default is @p FALSE. + * @note    The stack check is performed in a architecture/port dependent way. + *          It may not be implemented or some ports. + * @note    The default failure mode is to halt the system with the global + *          @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK           FALSE +#endif + +/** + * @brief   Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + *          value when a thread is created. This can be useful for the + *          runtime measurement of the used stack. + * + * @note    The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS                 FALSE +#endif + +/** + * @brief   Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + *          counts the system ticks occurred while executing the thread. + * + * @note    The default is @p FALSE. + * @note    This debug option is not currently compatible with the + *          tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING            FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief   System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS                                          \ +  /* Add threads custom fields here.*/ + +/** + * @brief   System initialization hook. + * @details User initialization code added to the @p chSysInit() function + *          just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() {                                         \ +  /* Add threads initialization code here.*/                                \ +} + +/** + * @brief   Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS                                          \ +  /* Add threads custom fields here.*/ + +/** + * @brief   Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note    It is invoked from within @p _thread_init() and implicitly from all + *          the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) {                                       \ +  /* Add threads initialization code here.*/                                \ +} + +/** + * @brief   Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) {                                       \ +  /* Add threads finalization code here.*/                                  \ +} + +/** + * @brief   Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) {                              \ +  /* Context switch code here.*/                                            \ +} + +/** + * @brief   ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() {                                        \ +  /* IRQ prologue code here.*/                                              \ +} + +/** + * @brief   ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() {                                        \ +  /* IRQ epilogue code here.*/                                              \ +} + +/** + * @brief   Idle thread enter hook. + * @note    This hook is invoked within a critical zone, no OS functions + *          should be invoked from here. + * @note    This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() {                                          \ +  /* Idle-enter code here.*/                                                \ +} + +/** + * @brief   Idle thread leave hook. + * @note    This hook is invoked within a critical zone, no OS functions + *          should be invoked from here. + * @note    This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() {                                          \ +  /* Idle-leave code here.*/                                                \ +} + +/** + * @brief   Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() {                                           \ +  /* Idle loop code here.*/                                                 \ +} + +/** + * @brief   System tick event hook. + * @details This hook is invoked in the system tick handler immediately + *          after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() {                                         \ +  /* System tick event code here.*/                                         \ +} + +/** + * @brief   System halt hook. + * @details This hook is invoked in case to a system halting error before + *          the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) {                                   \ +  /* System halt code here.*/                                               \ +} + +/** + * @brief   Trace hook. + * @details This hook is invoked each time a new record is written in the + *          trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) {                                            \ +  /* Trace code here.*/                                                     \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h).    */ +/*===========================================================================*/ + +#endif  /* CHCONF_H */ + +/** @} */ diff --git a/platforms/chibios/BLACKPILL_STM32_F401/configs/config.h b/platforms/chibios/BLACKPILL_STM32_F401/configs/config.h new file mode 100644 index 0000000000..eb73e72ef2 --- /dev/null +++ b/platforms/chibios/BLACKPILL_STM32_F401/configs/config.h @@ -0,0 +1,23 @@ +/* Copyright 2020 Nick Brassel (tzarc) + * + *  This program is free software: you can redistribute it and/or modify + *  it under the terms of the GNU General Public License as published by + *  the Free Software Foundation, either version 3 of the License, or + *  (at your option) any later version. + * + *  This program is distributed in the hope that it will be useful, + *  but WITHOUT ANY WARRANTY; without even the implied warranty of + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the + *  GNU General Public License for more details. + * + *  You should have received a copy of the GNU General Public License + *  along with this program.  If not, see <https://www.gnu.org/licenses/>. + */ +#pragma once + +#define BOARD_OTG_NOVBUSSENS 1 + +#define STM32_LSECLK 32768U +#define STM32_HSECLK 25000000U + +#define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE diff --git a/platforms/chibios/BLACKPILL_STM32_F401/configs/halconf.h b/platforms/chibios/BLACKPILL_STM32_F401/configs/halconf.h new file mode 100644 index 0000000000..a8db392aaa --- /dev/null +++ b/platforms/chibios/BLACKPILL_STM32_F401/configs/halconf.h @@ -0,0 +1,525 @@ +/* +    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + +    Licensed under the Apache License, Version 2.0 (the "License"); +    you may not use this file except in compliance with the License. +    You may obtain a copy of the License at + +        http://www.apache.org/licenses/LICENSE-2.0 + +    Unless required by applicable law or agreed to in writing, software +    distributed under the License is distributed on an "AS IS" BASIS, +    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +    See the License for the specific language governing permissions and +    limitations under the License. +*/ + +/** + * @file    templates/halconf.h + * @brief   HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + *          various device drivers from your application. You may also use + *          this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_7_0_ + +#include "mcuconf.h" + +/** + * @brief   Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL                         TRUE +#endif + +/** + * @brief   Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC                         FALSE +#endif + +/** + * @brief   Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN                         FALSE +#endif + +/** + * @brief   Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY                         FALSE +#endif + +/** + * @brief   Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC                         FALSE +#endif + +/** + * @brief   Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT                         FALSE +#endif + +/** + * @brief   Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C                         FALSE +#endif + +/** + * @brief   Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S                         FALSE +#endif + +/** + * @brief   Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU                         FALSE +#endif + +/** + * @brief   Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC                         FALSE +#endif + +/** + * @brief   Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI                     FALSE +#endif + +/** + * @brief   Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM                         FALSE +#endif + +/** + * @brief   Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC                         FALSE +#endif + +/** + * @brief   Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC                         FALSE +#endif + +/** + * @brief   Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL                      FALSE +#endif + +/** + * @brief   Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB                  FALSE +#endif + +/** + * @brief   Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO                         FALSE +#endif + +/** + * @brief   Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI                         FALSE +#endif + +/** + * @brief   Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG                        FALSE +#endif + +/** + * @brief   Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART                        FALSE +#endif + +/** + * @brief   Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB                         TRUE +#endif + +/** + * @brief   Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG                         FALSE +#endif + +/** + * @brief   Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI                        FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings.                                              */ +/*===========================================================================*/ + +/** + * @brief   Enables synchronous APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS                   FALSE +#endif + +/** + * @brief   Enables synchronous APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT                        FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings.                                              */ +/*===========================================================================*/ + +/** + * @brief   Enables synchronous APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT                        TRUE +#endif + +/** + * @brief   Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION            TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings.                                              */ +/*===========================================================================*/ + +/** + * @brief   Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE                  TRUE +#endif + +/** + * @brief   Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS           FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings.                                              */ +/*===========================================================================*/ + +/** + * @brief   Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + *          implementation for algorithms not supported by the underlying + *          hardware. + * @note    Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK                FALSE +#endif + +/** + * @brief   Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK            FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings.                                              */ +/*===========================================================================*/ + +/** + * @brief   Enables synchronous APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT                        TRUE +#endif + +/** + * @brief   Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION            TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings.                                              */ +/*===========================================================================*/ + +/** + * @brief   Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION            TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings.                                              */ +/*===========================================================================*/ + +/** + * @brief   Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY                   FALSE +#endif + +/** + * @brief   Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS                      TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings.                                          */ +/*===========================================================================*/ + +/** + * @brief   Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + *          routines releasing some extra CPU time for the threads with + *          lower priority, this may slow down the driver a bit however. + *          This option is recommended also if the SPI driver does not + *          use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING                    TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings.                                              */ +/*===========================================================================*/ + +/** + * @brief   Number of initialization attempts before rejecting the card. + * @note    Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY                      100 +#endif + +/** + * @brief   Include support for MMC cards. + * @note    MMC support is not yet implemented so this option must be kept + *          at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT                     FALSE +#endif + +/** + * @brief   Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + *          routines releasing some extra CPU time for the threads with + *          lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING                    TRUE +#endif + +/** + * @brief   OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20                    0x50FF8000U +#endif + +/** + * @brief   OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR                        0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings.                                           */ +/*===========================================================================*/ + +/** + * @brief   Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + *          default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE              38400 +#endif + +/** + * @brief   Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + *          buffers depending on the requirements of your application. + * @note    The default is 16 bytes for both the transmission and receive + *          buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE                 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting.                                        */ +/*===========================================================================*/ + +/** + * @brief   Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + *          the USB data endpoint maximum packet size. + * @note    The default is 256 bytes for both the transmission and receive + *          buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE             256 +#endif + +/** + * @brief   Serial over USB number of buffers. + * @note    The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER           2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings.                                              */ +/*===========================================================================*/ + +/** + * @brief   Enables synchronous APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT                        TRUE +#endif + +/** + * @brief   Enables circular transfers APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR                    FALSE +#endif + + +/** + * @brief   Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION            TRUE +#endif + +/** + * @brief   Handling method for SPI CS line. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE                     SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings.                                             */ +/*===========================================================================*/ + +/** + * @brief   Enables synchronous APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT                       FALSE +#endif + +/** + * @brief   Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION           FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings.                                              */ +/*===========================================================================*/ + +/** + * @brief   Enables synchronous APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT                        TRUE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings.                                             */ +/*===========================================================================*/ + +/** + * @brief   Enables synchronous APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT                       TRUE +#endif + +/** + * @brief   Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION           TRUE +#endif + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/platforms/chibios/BLACKPILL_STM32_F401/configs/mcuconf.h b/platforms/chibios/BLACKPILL_STM32_F401/configs/mcuconf.h new file mode 100644 index 0000000000..ba6e934fe7 --- /dev/null +++ b/platforms/chibios/BLACKPILL_STM32_F401/configs/mcuconf.h @@ -0,0 +1,253 @@ +/* +    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + +    Licensed under the Apache License, Version 2.0 (the "License"); +    you may not use this file except in compliance with the License. +    You may obtain a copy of the License at + +        http://www.apache.org/licenses/LICENSE-2.0 + +    Unless required by applicable law or agreed to in writing, software +    distributed under the License is distributed on an "AS IS" BASIS, +    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +    See the License for the specific language governing permissions and +    limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0       Lowest...Highest. + * + * DMA priorities: + * 0...3        Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT                       FALSE +#define STM32_HSI_ENABLED                   TRUE +#define STM32_LSI_ENABLED                   TRUE +#define STM32_HSE_ENABLED                   TRUE +#define STM32_LSE_ENABLED                   FALSE +#define STM32_CLOCK48_REQUIRED              TRUE +#define STM32_SW                            STM32_SW_PLL +#define STM32_PLLSRC                        STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE                    25        +#define STM32_PLLN_VALUE                    336      +#define STM32_PLLP_VALUE                    4        +#define STM32_PLLQ_VALUE                    7        +#define STM32_HPRE                          STM32_HPRE_DIV1   +#define STM32_PPRE1                         STM32_PPRE1_DIV4   +#define STM32_PPRE2                         STM32_PPRE2_DIV2  +#define STM32_RTCSEL                        STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE                  8 +#define STM32_MCO1SEL                       STM32_MCO1SEL_HSI +#define STM32_MCO1PRE                       STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL                       STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE                       STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC                        STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE                 192 +#define STM32_PLLI2SR_VALUE                 5 +#define STM32_PVD_ENABLE                    FALSE +#define STM32_PLS                           STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE                 FALSE + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY            6 +#define STM32_IRQ_EXTI1_PRIORITY            6 +#define STM32_IRQ_EXTI2_PRIORITY            6 +#define STM32_IRQ_EXTI3_PRIORITY            6 +#define STM32_IRQ_EXTI4_PRIORITY            6 +#define STM32_IRQ_EXTI5_9_PRIORITY          6 +#define STM32_IRQ_EXTI10_15_PRIORITY        6 +#define STM32_IRQ_EXTI16_PRIORITY           6 +#define STM32_IRQ_EXTI17_PRIORITY           15 +#define STM32_IRQ_EXTI18_PRIORITY           6 +#define STM32_IRQ_EXTI19_PRIORITY           6 +#define STM32_IRQ_EXTI20_PRIORITY           6 +#define STM32_IRQ_EXTI21_PRIORITY           15 +#define STM32_IRQ_EXTI22_PRIORITY           15 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE                    ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1                  FALSE +#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC1_DMA_PRIORITY         2 +#define STM32_ADC_IRQ_PRIORITY              6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1                  FALSE +#define STM32_GPT_USE_TIM2                  FALSE +#define STM32_GPT_USE_TIM3                  FALSE +#define STM32_GPT_USE_TIM4                  FALSE +#define STM32_GPT_USE_TIM5                  FALSE +#define STM32_GPT_USE_TIM9                  FALSE +#define STM32_GPT_USE_TIM11                 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY         7 +#define STM32_GPT_TIM2_IRQ_PRIORITY         7 +#define STM32_GPT_TIM3_IRQ_PRIORITY         7 +#define STM32_GPT_TIM4_IRQ_PRIORITY         7 +#define STM32_GPT_TIM5_IRQ_PRIORITY         7 +#define STM32_GPT_TIM9_IRQ_PRIORITY         7 +#define STM32_GPT_TIM11_IRQ_PRIORITY        7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1                  FALSE +#define STM32_I2C_USE_I2C2                  FALSE +#define STM32_I2C_USE_I2C3                  FALSE +#define STM32_I2C_BUSY_TIMEOUT              50 +#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY         5 +#define STM32_I2C_I2C2_IRQ_PRIORITY         5 +#define STM32_I2C_I2C3_IRQ_PRIORITY         5 +#define STM32_I2C_I2C1_DMA_PRIORITY         3 +#define STM32_I2C_I2C2_DMA_PRIORITY         3 +#define STM32_I2C_I2C3_DMA_PRIORITY         3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp)      osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI2                  FALSE +#define STM32_I2S_USE_SPI3                  FALSE +#define STM32_I2S_SPI2_IRQ_PRIORITY         10 +#define STM32_I2S_SPI3_IRQ_PRIORITY         10 +#define STM32_I2S_SPI2_DMA_PRIORITY         1 +#define STM32_I2S_SPI3_DMA_PRIORITY         1 +#define STM32_I2S_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2S_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp)      osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1                  FALSE +#define STM32_ICU_USE_TIM2                  FALSE +#define STM32_ICU_USE_TIM3                  FALSE +#define STM32_ICU_USE_TIM4                  FALSE +#define STM32_ICU_USE_TIM5                  FALSE +#define STM32_ICU_USE_TIM9                  FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY         7 +#define STM32_ICU_TIM2_IRQ_PRIORITY         7 +#define STM32_ICU_TIM3_IRQ_PRIORITY         7 +#define STM32_ICU_TIM4_IRQ_PRIORITY         7 +#define STM32_ICU_TIM5_IRQ_PRIORITY         7 +#define STM32_ICU_TIM9_IRQ_PRIORITY         7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED              FALSE +#define STM32_PWM_USE_TIM1                  FALSE +#define STM32_PWM_USE_TIM2                  FALSE +#define STM32_PWM_USE_TIM3                  FALSE +#define STM32_PWM_USE_TIM4                  FALSE +#define STM32_PWM_USE_TIM5                  FALSE +#define STM32_PWM_USE_TIM9                  FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY         7 +#define STM32_PWM_TIM2_IRQ_PRIORITY         7 +#define STM32_PWM_TIM3_IRQ_PRIORITY         7 +#define STM32_PWM_TIM4_IRQ_PRIORITY         7 +#define STM32_PWM_TIM5_IRQ_PRIORITY         7 +#define STM32_PWM_TIM9_IRQ_PRIORITY         7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1             FALSE +#define STM32_SERIAL_USE_USART2             FALSE +#define STM32_SERIAL_USE_USART6             FALSE +#define STM32_SERIAL_USART1_PRIORITY        12 +#define STM32_SERIAL_USART2_PRIORITY        12 +#define STM32_SERIAL_USART6_PRIORITY        12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1                  FALSE +#define STM32_SPI_USE_SPI2                  FALSE +#define STM32_SPI_USE_SPI3                  FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY         1 +#define STM32_SPI_SPI2_DMA_PRIORITY         1 +#define STM32_SPI_SPI3_DMA_PRIORITY         1 +#define STM32_SPI_SPI1_IRQ_PRIORITY         10 +#define STM32_SPI_SPI2_IRQ_PRIORITY         10 +#define STM32_SPI_SPI3_IRQ_PRIORITY         10 +#define STM32_SPI_DMA_ERROR_HOOK(spip)      osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY               8 +#define STM32_ST_USE_TIMER                  2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1               FALSE +#define STM32_UART_USE_USART2               FALSE +#define STM32_UART_USE_USART6               FALSE +#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART6_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY      12 +#define STM32_UART_USART2_IRQ_PRIORITY      12 +#define STM32_UART_USART6_IRQ_PRIORITY      12 +#define STM32_UART_USART1_DMA_PRIORITY      0 +#define STM32_UART_USART2_DMA_PRIORITY      0 +#define STM32_UART_USART6_DMA_PRIORITY      0 +#define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1                  TRUE +#define STM32_USB_OTG1_IRQ_PRIORITY         14 +#define STM32_USB_OTG1_RX_FIFO_SIZE         512 +#define STM32_USB_OTG_THREAD_PRIO           NORMALPRIO+1 +#define STM32_USB_OTG_THREAD_STACK_SIZE     128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI      0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG                  FALSE + +#endif /* MCUCONF_H */ diff --git a/platforms/chibios/BLACKPILL_STM32_F411/board/board.mk b/platforms/chibios/BLACKPILL_STM32_F411/board/board.mk new file mode 100644 index 0000000000..bb00b1a2b0 --- /dev/null +++ b/platforms/chibios/BLACKPILL_STM32_F411/board/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F411RE/board.c + +# Required include directories +BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F411RE + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC  += $(BOARDINC) diff --git a/platforms/chibios/BLACKPILL_STM32_F411/configs/board.h b/platforms/chibios/BLACKPILL_STM32_F411/configs/board.h new file mode 100644 index 0000000000..30af6b0c86 --- /dev/null +++ b/platforms/chibios/BLACKPILL_STM32_F411/configs/board.h @@ -0,0 +1,20 @@ +/* Copyright 2020 Nick Brassel (tzarc) + * + *  This program is free software: you can redistribute it and/or modify + *  it under the terms of the GNU General Public License as published by + *  the Free Software Foundation, either version 3 of the License, or + *  (at your option) any later version. + * + *  This program is distributed in the hope that it will be useful, + *  but WITHOUT ANY WARRANTY; without even the implied warranty of + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the + *  GNU General Public License for more details. + * + *  You should have received a copy of the GNU General Public License + *  along with this program.  If not, see <https://www.gnu.org/licenses/>. + */ +#pragma once + +#include_next "board.h" + +#undef STM32_HSE_BYPASS diff --git a/platforms/chibios/BLACKPILL_STM32_F411/configs/chconf.h b/platforms/chibios/BLACKPILL_STM32_F411/configs/chconf.h new file mode 100644 index 0000000000..7dc4f84a8a --- /dev/null +++ b/platforms/chibios/BLACKPILL_STM32_F411/configs/chconf.h @@ -0,0 +1,714 @@ +/* +    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + +    Licensed under the Apache License, Version 2.0 (the "License"); +    you may not use this file except in compliance with the License. +    You may obtain a copy of the License at + +        http://www.apache.org/licenses/LICENSE-2.0 + +    Unless required by applicable law or agreed to in writing, software +    distributed under the License is distributed on an "AS IS" BASIS, +    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +    See the License for the specific language governing permissions and +    limitations under the License. +*/ + +/** + * @file    rt/templates/chconf.h + * @brief   Configuration file template. + * @details A copy of this file must be placed in each project directory, it + *          contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_6_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief   System time counter resolution. + * @note    Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION                32 +#endif + +/** + * @brief   System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + *          setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY                 10000 +#endif + +/** + * @brief   Time intervals data size. + * @note    Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE               32 +#endif + +/** + * @brief   Time types data size. + * @note    Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE              32 +#endif + +/** + * @brief   Time delta constant for the tick-less mode. + * @note    If this value is zero then the system uses the classic + *          periodic tick. This value represents the minimum number + *          of ticks that is safe to specify in a timeout directive. + *          The value one is not valid, timeouts are rounded up to + *          this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA                 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief   Round robin interval. + * @details This constant is the number of system ticks allowed for the + *          threads before preemption occurs. Setting this value to zero + *          disables the preemption for threads with equal priority and the + *          round robin becomes cooperative. Note that higher priority + *          threads can still preempt, the kernel is always preemptive. + * @note    Disabling the round robin preemption makes the kernel more compact + *          and generally faster. + * @note    The round robin preemption is not supported in tickless mode and + *          must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM                 0 +#endif + +/** + * @brief   Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + *          then the whole available RAM is used. The core memory is made + *          available to the heap allocator and/or can be used directly through + *          the simplified core memory allocator. + * + * @note    In order to let the OS manage the whole RAM the linker script must + *          provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note    Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE                 0 +#endif + +/** + * @brief   Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + *          does not spawn the idle thread. The application @p main() + *          function becomes the idle thread and must implement an + *          infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD               FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief   OS optimization. + * @details If enabled then time efficient rather than space efficient code + *          is used when two possible implementations exist. + * + * @note    This is not related to the compiler optimization options. + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED               TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief   Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + *          the kernel. + * + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM                       TRUE +#endif + +/** + * @brief   Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY                 TRUE +#endif + +/** + * @brief   Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + *          the kernel. + * + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT                 TRUE +#endif + +/** + * @brief   Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES               TRUE +#endif + +/** + * @brief   Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + *          priority rather than in FIFO order. + * + * @note    The default is @p FALSE. Enable this if you have special + *          requirements. + * @note    Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY      FALSE +#endif + +/** + * @brief   Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES                  TRUE +#endif + +/** + * @brief   Enables recursive behavior on mutexes. + * @note    Recursive mutexes are heavier and have an increased + *          memory footprint. + * + * @note    The default is @p FALSE. + * @note    Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE        FALSE +#endif + +/** + * @brief   Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + *          in the kernel. + * + * @note    The default is @p TRUE. + * @note    Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS                 TRUE +#endif + +/** + * @brief   Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + *          specification are included in the kernel. + * + * @note    The default is @p TRUE. + * @note    Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT         TRUE +#endif + +/** + * @brief   Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS                   TRUE +#endif + +/** + * @brief   Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + *          are included in the kernel. + * + * @note    The default is @p TRUE. + * @note    Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT           TRUE +#endif + +/** + * @brief   Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + *          in the kernel. + * + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES                 TRUE +#endif + +/** + * @brief   Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + *          FIFO order. + * + * @note    The default is @p FALSE. Enable this if you have special + *          requirements. + * @note    Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY        FALSE +#endif + +/** + * @brief   Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + *          included in the kernel. + * + * @note    The default is @p TRUE. + * @note    Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES                TRUE +#endif + +/** + * @brief   Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + *          in the kernel. + * + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE                  TRUE +#endif + +/** + * @brief   Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + *          in the kernel. + * + * @note    The default is @p TRUE. + * @note    Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + *          @p CH_CFG_USE_SEMAPHORES. + * @note    Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP                     TRUE +#endif + +/** + * @brief   Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + *          in the kernel. + * + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS                 TRUE +#endif + +/** + * @brief   Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + *          in the kernel. + * + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS                TRUE +#endif + +/** + * @brief   Pipes APIs. + * @details If enabled then the pipes APIs are included + *          in the kernel. + * + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES                    TRUE +#endif + +/** + * @brief   Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + *          in the kernel. + * + * @note    The default is @p TRUE. + * @note    Requires @p CH_CFG_USE_WAITEXIT. + * @note    Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC                  TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief   Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + *          kernel. + * + * @note    The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY                  TRUE +#endif + +/** + * @brief   Maximum length for object names. + * @details If the specified length is zero then the name is stored by + *          pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH     8 +#endif + +/** + * @brief   Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY     TRUE +#endif + +/** + * @brief   Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS      TRUE +#endif + +/** + * @brief   Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES           TRUE +#endif + +/** + * @brief   Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES            TRUE +#endif + +/** + * @brief   Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS            TRUE +#endif + +/** + * @brief   Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES                TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief   Debug option, kernel statistics. + * + * @note    The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS                   FALSE +#endif + +/** + * @brief   Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + *          at runtime. + * + * @note    The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK           FALSE +#endif + +/** + * @brief   Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + *          parameters are activated. + * + * @note    The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS                FALSE +#endif + +/** + * @brief   Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + *          activated. This includes consistency checks inside the kernel, + *          runtime anomalies and port-defined checks. + * + * @note    The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS               FALSE +#endif + +/** + * @brief   Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note    The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK                   CH_DBG_TRACE_MASK_DISABLED +#endif + +/** + * @brief   Trace buffer entries. + * @note    The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + *          different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE            128 +#endif + +/** + * @brief   Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note    The default is @p FALSE. + * @note    The stack check is performed in a architecture/port dependent way. + *          It may not be implemented or some ports. + * @note    The default failure mode is to halt the system with the global + *          @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK           FALSE +#endif + +/** + * @brief   Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + *          value when a thread is created. This can be useful for the + *          runtime measurement of the used stack. + * + * @note    The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS                 FALSE +#endif + +/** + * @brief   Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + *          counts the system ticks occurred while executing the thread. + * + * @note    The default is @p FALSE. + * @note    This debug option is not currently compatible with the + *          tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING            FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief   System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS                                          \ +  /* Add threads custom fields here.*/ + +/** + * @brief   System initialization hook. + * @details User initialization code added to the @p chSysInit() function + *          just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() {                                         \ +  /* Add threads initialization code here.*/                                \ +} + +/** + * @brief   Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS                                          \ +  /* Add threads custom fields here.*/ + +/** + * @brief   Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note    It is invoked from within @p _thread_init() and implicitly from all + *          the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) {                                       \ +  /* Add threads initialization code here.*/                                \ +} + +/** + * @brief   Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) {                                       \ +  /* Add threads finalization code here.*/                                  \ +} + +/** + * @brief   Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) {                              \ +  /* Context switch code here.*/                                            \ +} + +/** + * @brief   ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() {                                        \ +  /* IRQ prologue code here.*/                                              \ +} + +/** + * @brief   ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() {                                        \ +  /* IRQ epilogue code here.*/                                              \ +} + +/** + * @brief   Idle thread enter hook. + * @note    This hook is invoked within a critical zone, no OS functions + *          should be invoked from here. + * @note    This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() {                                          \ +  /* Idle-enter code here.*/                                                \ +} + +/** + * @brief   Idle thread leave hook. + * @note    This hook is invoked within a critical zone, no OS functions + *          should be invoked from here. + * @note    This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() {                                          \ +  /* Idle-leave code here.*/                                                \ +} + +/** + * @brief   Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() {                                           \ +  /* Idle loop code here.*/                                                 \ +} + +/** + * @brief   System tick event hook. + * @details This hook is invoked in the system tick handler immediately + *          after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() {                                         \ +  /* System tick event code here.*/                                         \ +} + +/** + * @brief   System halt hook. + * @details This hook is invoked in case to a system halting error before + *          the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) {                                   \ +  /* System halt code here.*/                                               \ +} + +/** + * @brief   Trace hook. + * @details This hook is invoked each time a new record is written in the + *          trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) {                                            \ +  /* Trace code here.*/                                                     \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h).    */ +/*===========================================================================*/ + +#endif  /* CHCONF_H */ + +/** @} */ diff --git a/platforms/chibios/BLACKPILL_STM32_F411/configs/config.h b/platforms/chibios/BLACKPILL_STM32_F411/configs/config.h new file mode 100644 index 0000000000..eb73e72ef2 --- /dev/null +++ b/platforms/chibios/BLACKPILL_STM32_F411/configs/config.h @@ -0,0 +1,23 @@ +/* Copyright 2020 Nick Brassel (tzarc) + * + *  This program is free software: you can redistribute it and/or modify + *  it under the terms of the GNU General Public License as published by + *  the Free Software Foundation, either version 3 of the License, or + *  (at your option) any later version. + * + *  This program is distributed in the hope that it will be useful, + *  but WITHOUT ANY WARRANTY; without even the implied warranty of + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the + *  GNU General Public License for more details. + * + *  You should have received a copy of the GNU General Public License + *  along with this program.  If not, see <https://www.gnu.org/licenses/>. + */ +#pragma once + +#define BOARD_OTG_NOVBUSSENS 1 + +#define STM32_LSECLK 32768U +#define STM32_HSECLK 25000000U + +#define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE diff --git a/platforms/chibios/BLACKPILL_STM32_F411/configs/halconf.h b/platforms/chibios/BLACKPILL_STM32_F411/configs/halconf.h new file mode 100644 index 0000000000..a8db392aaa --- /dev/null +++ b/platforms/chibios/BLACKPILL_STM32_F411/configs/halconf.h @@ -0,0 +1,525 @@ +/* +    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + +    Licensed under the Apache License, Version 2.0 (the "License"); +    you may not use this file except in compliance with the License. +    You may obtain a copy of the License at + +        http://www.apache.org/licenses/LICENSE-2.0 + +    Unless required by applicable law or agreed to in writing, software +    distributed under the License is distributed on an "AS IS" BASIS, +    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +    See the License for the specific language governing permissions and +    limitations under the License. +*/ + +/** + * @file    templates/halconf.h + * @brief   HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + *          various device drivers from your application. You may also use + *          this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_7_0_ + +#include "mcuconf.h" + +/** + * @brief   Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL                         TRUE +#endif + +/** + * @brief   Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC                         FALSE +#endif + +/** + * @brief   Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN                         FALSE +#endif + +/** + * @brief   Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY                         FALSE +#endif + +/** + * @brief   Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC                         FALSE +#endif + +/** + * @brief   Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT                         FALSE +#endif + +/** + * @brief   Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C                         FALSE +#endif + +/** + * @brief   Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S                         FALSE +#endif + +/** + * @brief   Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU                         FALSE +#endif + +/** + * @brief   Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC                         FALSE +#endif + +/** + * @brief   Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI                     FALSE +#endif + +/** + * @brief   Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM                         FALSE +#endif + +/** + * @brief   Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC                         FALSE +#endif + +/** + * @brief   Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC                         FALSE +#endif + +/** + * @brief   Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL                      FALSE +#endif + +/** + * @brief   Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB                  FALSE +#endif + +/** + * @brief   Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO                         FALSE +#endif + +/** + * @brief   Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI                         FALSE +#endif + +/** + * @brief   Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG                        FALSE +#endif + +/** + * @brief   Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART                        FALSE +#endif + +/** + * @brief   Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB                         TRUE +#endif + +/** + * @brief   Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG                         FALSE +#endif + +/** + * @brief   Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI                        FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings.                                              */ +/*===========================================================================*/ + +/** + * @brief   Enables synchronous APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS                   FALSE +#endif + +/** + * @brief   Enables synchronous APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT                        FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings.                                              */ +/*===========================================================================*/ + +/** + * @brief   Enables synchronous APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT                        TRUE +#endif + +/** + * @brief   Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION            TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings.                                              */ +/*===========================================================================*/ + +/** + * @brief   Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE                  TRUE +#endif + +/** + * @brief   Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS           FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings.                                              */ +/*===========================================================================*/ + +/** + * @brief   Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + *          implementation for algorithms not supported by the underlying + *          hardware. + * @note    Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK                FALSE +#endif + +/** + * @brief   Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK            FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings.                                              */ +/*===========================================================================*/ + +/** + * @brief   Enables synchronous APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT                        TRUE +#endif + +/** + * @brief   Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION            TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings.                                              */ +/*===========================================================================*/ + +/** + * @brief   Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION            TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings.                                              */ +/*===========================================================================*/ + +/** + * @brief   Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY                   FALSE +#endif + +/** + * @brief   Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS                      TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings.                                          */ +/*===========================================================================*/ + +/** + * @brief   Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + *          routines releasing some extra CPU time for the threads with + *          lower priority, this may slow down the driver a bit however. + *          This option is recommended also if the SPI driver does not + *          use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING                    TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings.                                              */ +/*===========================================================================*/ + +/** + * @brief   Number of initialization attempts before rejecting the card. + * @note    Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY                      100 +#endif + +/** + * @brief   Include support for MMC cards. + * @note    MMC support is not yet implemented so this option must be kept + *          at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT                     FALSE +#endif + +/** + * @brief   Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + *          routines releasing some extra CPU time for the threads with + *          lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING                    TRUE +#endif + +/** + * @brief   OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20                    0x50FF8000U +#endif + +/** + * @brief   OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR                        0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings.                                           */ +/*===========================================================================*/ + +/** + * @brief   Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + *          default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE              38400 +#endif + +/** + * @brief   Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + *          buffers depending on the requirements of your application. + * @note    The default is 16 bytes for both the transmission and receive + *          buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE                 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting.                                        */ +/*===========================================================================*/ + +/** + * @brief   Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + *          the USB data endpoint maximum packet size. + * @note    The default is 256 bytes for both the transmission and receive + *          buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE             256 +#endif + +/** + * @brief   Serial over USB number of buffers. + * @note    The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER           2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings.                                              */ +/*===========================================================================*/ + +/** + * @brief   Enables synchronous APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT                        TRUE +#endif + +/** + * @brief   Enables circular transfers APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR                    FALSE +#endif + + +/** + * @brief   Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION            TRUE +#endif + +/** + * @brief   Handling method for SPI CS line. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE                     SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings.                                             */ +/*===========================================================================*/ + +/** + * @brief   Enables synchronous APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT                       FALSE +#endif + +/** + * @brief   Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION           FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings.                                              */ +/*===========================================================================*/ + +/** + * @brief   Enables synchronous APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT                        TRUE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings.                                             */ +/*===========================================================================*/ + +/** + * @brief   Enables synchronous APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT                       TRUE +#endif + +/** + * @brief   Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION           TRUE +#endif + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/platforms/chibios/BLACKPILL_STM32_F411/configs/mcuconf.h b/platforms/chibios/BLACKPILL_STM32_F411/configs/mcuconf.h new file mode 100644 index 0000000000..0394ff56bb --- /dev/null +++ b/platforms/chibios/BLACKPILL_STM32_F411/configs/mcuconf.h @@ -0,0 +1,253 @@ +/* +    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + +    Licensed under the Apache License, Version 2.0 (the "License"); +    you may not use this file except in compliance with the License. +    You may obtain a copy of the License at + +        http://www.apache.org/licenses/LICENSE-2.0 + +    Unless required by applicable law or agreed to in writing, software +    distributed under the License is distributed on an "AS IS" BASIS, +    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +    See the License for the specific language governing permissions and +    limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0       Lowest...Highest. + * + * DMA priorities: + * 0...3        Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT                       FALSE +#define STM32_HSI_ENABLED                   TRUE +#define STM32_LSI_ENABLED                   TRUE +#define STM32_HSE_ENABLED                   TRUE +#define STM32_LSE_ENABLED                   FALSE +#define STM32_CLOCK48_REQUIRED              TRUE +#define STM32_SW                            STM32_SW_PLL +#define STM32_PLLSRC                        STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE                    25 +#define STM32_PLLN_VALUE                    384 +#define STM32_PLLP_VALUE                    4 +#define STM32_PLLQ_VALUE                    8 +#define STM32_HPRE                          STM32_HPRE_DIV1 +#define STM32_PPRE1                         STM32_PPRE1_DIV4 +#define STM32_PPRE2                         STM32_PPRE2_DIV2 +#define STM32_RTCSEL                        STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE                  8 +#define STM32_MCO1SEL                       STM32_MCO1SEL_HSI +#define STM32_MCO1PRE                       STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL                       STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE                       STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC                        STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE                 192 +#define STM32_PLLI2SR_VALUE                 5 +#define STM32_PVD_ENABLE                    FALSE +#define STM32_PLS                           STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE                 FALSE + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY            6 +#define STM32_IRQ_EXTI1_PRIORITY            6 +#define STM32_IRQ_EXTI2_PRIORITY            6 +#define STM32_IRQ_EXTI3_PRIORITY            6 +#define STM32_IRQ_EXTI4_PRIORITY            6 +#define STM32_IRQ_EXTI5_9_PRIORITY          6 +#define STM32_IRQ_EXTI10_15_PRIORITY        6 +#define STM32_IRQ_EXTI16_PRIORITY           6 +#define STM32_IRQ_EXTI17_PRIORITY           15 +#define STM32_IRQ_EXTI18_PRIORITY           6 +#define STM32_IRQ_EXTI19_PRIORITY           6 +#define STM32_IRQ_EXTI20_PRIORITY           6 +#define STM32_IRQ_EXTI21_PRIORITY           15 +#define STM32_IRQ_EXTI22_PRIORITY           15 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE                    ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1                  FALSE +#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC1_DMA_PRIORITY         2 +#define STM32_ADC_IRQ_PRIORITY              6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1                  FALSE +#define STM32_GPT_USE_TIM2                  FALSE +#define STM32_GPT_USE_TIM3                  FALSE +#define STM32_GPT_USE_TIM4                  FALSE +#define STM32_GPT_USE_TIM5                  FALSE +#define STM32_GPT_USE_TIM9                  FALSE +#define STM32_GPT_USE_TIM11                 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY         7 +#define STM32_GPT_TIM2_IRQ_PRIORITY         7 +#define STM32_GPT_TIM3_IRQ_PRIORITY         7 +#define STM32_GPT_TIM4_IRQ_PRIORITY         7 +#define STM32_GPT_TIM5_IRQ_PRIORITY         7 +#define STM32_GPT_TIM9_IRQ_PRIORITY         7 +#define STM32_GPT_TIM11_IRQ_PRIORITY        7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1                  FALSE +#define STM32_I2C_USE_I2C2                  FALSE +#define STM32_I2C_USE_I2C3                  FALSE +#define STM32_I2C_BUSY_TIMEOUT              50 +#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY         5 +#define STM32_I2C_I2C2_IRQ_PRIORITY         5 +#define STM32_I2C_I2C3_IRQ_PRIORITY         5 +#define STM32_I2C_I2C1_DMA_PRIORITY         3 +#define STM32_I2C_I2C2_DMA_PRIORITY         3 +#define STM32_I2C_I2C3_DMA_PRIORITY         3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp)      osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI2                  FALSE +#define STM32_I2S_USE_SPI3                  FALSE +#define STM32_I2S_SPI2_IRQ_PRIORITY         10 +#define STM32_I2S_SPI3_IRQ_PRIORITY         10 +#define STM32_I2S_SPI2_DMA_PRIORITY         1 +#define STM32_I2S_SPI3_DMA_PRIORITY         1 +#define STM32_I2S_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2S_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp)      osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1                  FALSE +#define STM32_ICU_USE_TIM2                  FALSE +#define STM32_ICU_USE_TIM3                  FALSE +#define STM32_ICU_USE_TIM4                  FALSE +#define STM32_ICU_USE_TIM5                  FALSE +#define STM32_ICU_USE_TIM9                  FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY         7 +#define STM32_ICU_TIM2_IRQ_PRIORITY         7 +#define STM32_ICU_TIM3_IRQ_PRIORITY         7 +#define STM32_ICU_TIM4_IRQ_PRIORITY         7 +#define STM32_ICU_TIM5_IRQ_PRIORITY         7 +#define STM32_ICU_TIM9_IRQ_PRIORITY         7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED              FALSE +#define STM32_PWM_USE_TIM1                  FALSE +#define STM32_PWM_USE_TIM2                  FALSE +#define STM32_PWM_USE_TIM3                  FALSE +#define STM32_PWM_USE_TIM4                  FALSE +#define STM32_PWM_USE_TIM5                  FALSE +#define STM32_PWM_USE_TIM9                  FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY         7 +#define STM32_PWM_TIM2_IRQ_PRIORITY         7 +#define STM32_PWM_TIM3_IRQ_PRIORITY         7 +#define STM32_PWM_TIM4_IRQ_PRIORITY         7 +#define STM32_PWM_TIM5_IRQ_PRIORITY         7 +#define STM32_PWM_TIM9_IRQ_PRIORITY         7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1             FALSE +#define STM32_SERIAL_USE_USART2             FALSE +#define STM32_SERIAL_USE_USART6             FALSE +#define STM32_SERIAL_USART1_PRIORITY        12 +#define STM32_SERIAL_USART2_PRIORITY        12 +#define STM32_SERIAL_USART6_PRIORITY        12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1                  FALSE +#define STM32_SPI_USE_SPI2                  FALSE +#define STM32_SPI_USE_SPI3                  FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY         1 +#define STM32_SPI_SPI2_DMA_PRIORITY         1 +#define STM32_SPI_SPI3_DMA_PRIORITY         1 +#define STM32_SPI_SPI1_IRQ_PRIORITY         10 +#define STM32_SPI_SPI2_IRQ_PRIORITY         10 +#define STM32_SPI_SPI3_IRQ_PRIORITY         10 +#define STM32_SPI_DMA_ERROR_HOOK(spip)      osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY               8 +#define STM32_ST_USE_TIMER                  2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1               FALSE +#define STM32_UART_USE_USART2               FALSE +#define STM32_UART_USE_USART6               FALSE +#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART6_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY      12 +#define STM32_UART_USART2_IRQ_PRIORITY      12 +#define STM32_UART_USART6_IRQ_PRIORITY      12 +#define STM32_UART_USART1_DMA_PRIORITY      0 +#define STM32_UART_USART2_DMA_PRIORITY      0 +#define STM32_UART_USART6_DMA_PRIORITY      0 +#define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1                  TRUE +#define STM32_USB_OTG1_IRQ_PRIORITY         14 +#define STM32_USB_OTG1_RX_FIFO_SIZE         512 +#define STM32_USB_OTG_THREAD_PRIO           NORMALPRIO+1 +#define STM32_USB_OTG_THREAD_STACK_SIZE     128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI      0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG                  FALSE + +#endif /* MCUCONF_H */ diff --git a/platforms/chibios/GENERIC_STM32_F042X6/board/board.c b/platforms/chibios/GENERIC_STM32_F042X6/board/board.c new file mode 100644 index 0000000000..7d93b68f9c --- /dev/null +++ b/platforms/chibios/GENERIC_STM32_F042X6/board/board.c @@ -0,0 +1,269 @@ +/* +    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + +    Licensed under the Apache License, Version 2.0 (the "License"); +    you may not use this file except in compliance with the License. +    You may obtain a copy of the License at + +        http://www.apache.org/licenses/LICENSE-2.0 + +    Unless required by applicable law or agreed to in writing, software +    distributed under the License is distributed on an "AS IS" BASIS, +    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +    See the License for the specific language governing permissions and +    limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#include "hal.h" +#include "stm32_gpio.h" + +/*===========================================================================*/ +/* Driver local definitions.                                                 */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables.                                                */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types.                                         */ +/*===========================================================================*/ + +/** + * @brief   Type of STM32 GPIO port setup. + */ +typedef struct { +  uint32_t              moder; +  uint32_t              otyper; +  uint32_t              ospeedr; +  uint32_t              pupdr; +  uint32_t              odr; +  uint32_t              afrl; +  uint32_t              afrh; +} gpio_setup_t; + +/** + * @brief   Type of STM32 GPIO initialization data. + */ +typedef struct { +#if STM32_HAS_GPIOA || defined(__DOXYGEN__) +  gpio_setup_t          PAData; +#endif +#if STM32_HAS_GPIOB || defined(__DOXYGEN__) +  gpio_setup_t          PBData; +#endif +#if STM32_HAS_GPIOC || defined(__DOXYGEN__) +  gpio_setup_t          PCData; +#endif +#if STM32_HAS_GPIOD || defined(__DOXYGEN__) +  gpio_setup_t          PDData; +#endif +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) +  gpio_setup_t          PEData; +#endif +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) +  gpio_setup_t          PFData; +#endif +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) +  gpio_setup_t          PGData; +#endif +#if STM32_HAS_GPIOH || defined(__DOXYGEN__) +  gpio_setup_t          PHData; +#endif +#if STM32_HAS_GPIOI || defined(__DOXYGEN__) +  gpio_setup_t          PIData; +#endif +#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) +  gpio_setup_t          PJData; +#endif +#if STM32_HAS_GPIOK || defined(__DOXYGEN__) +  gpio_setup_t          PKData; +#endif +} gpio_config_t; + +/** + * @brief   STM32 GPIO static initialization data. + */ +static const gpio_config_t gpio_default_config = { +#if STM32_HAS_GPIOA +  {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, +   VAL_GPIOA_ODR,   VAL_GPIOA_AFRL,   VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB +  {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, +   VAL_GPIOB_ODR,   VAL_GPIOB_AFRL,   VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC +  {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, +   VAL_GPIOC_ODR,   VAL_GPIOC_AFRL,   VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD +  {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, +   VAL_GPIOD_ODR,   VAL_GPIOD_AFRL,   VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE +  {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, +   VAL_GPIOE_ODR,   VAL_GPIOE_AFRL,   VAL_GPIOE_AFRH}, +#endif +#if STM32_HAS_GPIOF +  {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, +   VAL_GPIOF_ODR,   VAL_GPIOF_AFRL,   VAL_GPIOF_AFRH}, +#endif +#if STM32_HAS_GPIOG +  {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, +   VAL_GPIOG_ODR,   VAL_GPIOG_AFRL,   VAL_GPIOG_AFRH}, +#endif +#if STM32_HAS_GPIOH +  {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, +   VAL_GPIOH_ODR,   VAL_GPIOH_AFRL,   VAL_GPIOH_AFRH}, +#endif +#if STM32_HAS_GPIOI +  {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, +   VAL_GPIOI_ODR,   VAL_GPIOI_AFRL,   VAL_GPIOI_AFRH}, +#endif +#if STM32_HAS_GPIOJ +  {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, +   VAL_GPIOJ_ODR,   VAL_GPIOJ_AFRL,   VAL_GPIOJ_AFRH}, +#endif +#if STM32_HAS_GPIOK +  {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, +   VAL_GPIOK_ODR,   VAL_GPIOK_AFRL,   VAL_GPIOK_AFRH} +#endif +}; + +/*===========================================================================*/ +/* Driver local functions.                                                   */ +/*===========================================================================*/ + +static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { + +  gpiop->OTYPER  = config->otyper; +  gpiop->OSPEEDR = config->ospeedr; +  gpiop->PUPDR   = config->pupdr; +  gpiop->ODR     = config->odr; +  gpiop->AFRL    = config->afrl; +  gpiop->AFRH    = config->afrh; +  gpiop->MODER   = config->moder; +} + +static void stm32_gpio_init(void) { + +  /* Enabling GPIO-related clocks, the mask comes from the +     registry header file.*/ +  rccResetAHB(STM32_GPIO_EN_MASK); +  rccEnableAHB(STM32_GPIO_EN_MASK, true); + +  /* Initializing all the defined GPIO ports.*/ +#if STM32_HAS_GPIOA +  gpio_init(GPIOA, &gpio_default_config.PAData); +#endif +#if STM32_HAS_GPIOB +  gpio_init(GPIOB, &gpio_default_config.PBData); +#endif +#if STM32_HAS_GPIOC +  gpio_init(GPIOC, &gpio_default_config.PCData); +#endif +#if STM32_HAS_GPIOD +  gpio_init(GPIOD, &gpio_default_config.PDData); +#endif +#if STM32_HAS_GPIOE +  gpio_init(GPIOE, &gpio_default_config.PEData); +#endif +#if STM32_HAS_GPIOF +  gpio_init(GPIOF, &gpio_default_config.PFData); +#endif +#if STM32_HAS_GPIOG +  gpio_init(GPIOG, &gpio_default_config.PGData); +#endif +#if STM32_HAS_GPIOH +  gpio_init(GPIOH, &gpio_default_config.PHData); +#endif +#if STM32_HAS_GPIOI +  gpio_init(GPIOI, &gpio_default_config.PIData); +#endif +#if STM32_HAS_GPIOJ +  gpio_init(GPIOJ, &gpio_default_config.PJData); +#endif +#if STM32_HAS_GPIOK +  gpio_init(GPIOK, &gpio_default_config.PKData); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers.                                                */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions.                                                */ +/*===========================================================================*/ + +__attribute__((weak)) void enter_bootloader_mode_if_requested(void) {} + +/** + * @brief   Early initialization code. + * @details GPIO ports and system clocks are initialized before everything + *          else. + */ +void __early_init(void) { +  enter_bootloader_mode_if_requested(); + +  stm32_gpio_init(); +  stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief   SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { + +  (void)sdcp; +  /* TODO: Fill the implementation.*/ +  return true; +} + +/** + * @brief   SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { + +  (void)sdcp; +  /* TODO: Fill the implementation.*/ +  return false; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief   MMC_SPI card detection. + */ +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { + +  (void)mmcp; +  /* TODO: Fill the implementation.*/ +  return true; +} + +/** + * @brief   MMC_SPI card write protection detection. + */ +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { + +  (void)mmcp; +  /* TODO: Fill the implementation.*/ +  return false; +} +#endif + +/** + * @brief   Board-specific initialization code. + * @todo    Add your board-specific code, if any. + */ +void boardInit(void) { + +} diff --git a/platforms/chibios/GENERIC_STM32_F042X6/board/board.h b/platforms/chibios/GENERIC_STM32_F042X6/board/board.h new file mode 100644 index 0000000000..ee9d31e04a --- /dev/null +++ b/platforms/chibios/GENERIC_STM32_F042X6/board/board.h @@ -0,0 +1,896 @@ +/* +    ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + +    Licensed under the Apache License, Version 2.0 (the "License"); +    you may not use this file except in compliance with the License. +    You may obtain a copy of the License at + +        http://www.apache.org/licenses/LICENSE-2.0 + +    Unless required by applicable law or agreed to in writing, software +    distributed under the License is distributed on an "AS IS" BASIS, +    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +    See the License for the specific language governing permissions and +    limitations under the License. +*/ +#ifndef _BOARD_H +#define _BOARD_H + +/* + * Setup for STMicroelectronics STM32 Nucleo32-F042K6 board. + */ + +/* + * Board identifier. + */ +#define BOARD_GENERIC_STM32_F042X6 +#define BOARD_NAME                  "Generic STM32F042 PCB" + +/* + * Board oscillators-related settings. + * NOTE: LSE not fitted. + * NOTE: HSE not fitted. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK                0U +#endif + +#define STM32_LSEDRV                (3U << 3U) + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK                0U +#endif + +/* + * MCU type as defined in the ST header. + */ +#define STM32F042x6 + +/* + * IO pins assignments. + */ +#define GPIOA_PIN0                  0U +#define GPIOA_PIN1                  1U +#define GPIOA_PIN2                  2U +#define GPIOA_PIN3                  3U +#define GPIOA_PIN4                  4U +#define GPIOA_PIN5                  5U +#define GPIOA_PIN6                  6U +#define GPIOA_PIN7                  7U +#define GPIOA_PIN8                  8U +#define GPIOA_PIN9                  9U +#define GPIOA_PIN10                 10U +#define GPIOA_PIN11                11U +#define GPIOA_PIN12                12U +#define GPIOA_PIN13                 13U +#define GPIOA_PIN14                 14U +#define GPIOA_PIN15                 15U + +#define GPIOB_PIN0                  0U +#define GPIOB_PIN1                  1U +#define GPIOB_PIN2                  2U +#define GPIOB_PIN3                  3U +#define GPIOB_PIN4                  4U +#define GPIOB_PIN5                  5U +#define GPIOB_PIN6                  6U +#define GPIOB_PIN7                  7U +#define GPIOB_PIN8                  8U +#define GPIOB_PIN9                  9U +#define GPIOB_PIN10                 10U +#define GPIOB_PIN11                 11U +#define GPIOB_PIN12                 12U +#define GPIOB_PIN13                 13U +#define GPIOB_PIN14                 14U +#define GPIOB_PIN15                 15U + +#define GPIOC_PIN0                  0U +#define GPIOC_PIN1                  1U +#define GPIOC_PIN2                  2U +#define GPIOC_PIN3                  3U +#define GPIOC_PIN4                  4U +#define GPIOC_PIN5                  5U +#define GPIOC_PIN6                  6U +#define GPIOC_PIN7                  7U +#define GPIOC_PIN8                  8U +#define GPIOC_PIN9                  9U +#define GPIOC_PIN10                 10U +#define GPIOC_PIN11                 11U +#define GPIOC_PIN12                 12U +#define GPIOC_PIN13                 13U +#define GPIOC_PIN14                 14U +#define GPIOC_PIN15                 15U + +#define GPIOD_PIN0                  0U +#define GPIOD_PIN1                  1U +#define GPIOD_PIN2                  2U +#define GPIOD_PIN3                  3U +#define GPIOD_PIN4                  4U +#define GPIOD_PIN5                  5U +#define GPIOD_PIN6                  6U +#define GPIOD_PIN7                  7U +#define GPIOD_PIN8                  8U +#define GPIOD_PIN9                  9U +#define GPIOD_PIN10                 10U +#define GPIOD_PIN11                 11U +#define GPIOD_PIN12                 12U +#define GPIOD_PIN13                 13U +#define GPIOD_PIN14                 14U +#define GPIOD_PIN15                 15U + +#define GPIOE_PIN0                  0U +#define GPIOE_PIN1                  1U +#define GPIOE_PIN2                  2U +#define GPIOE_PIN3                  3U +#define GPIOE_PIN4                  4U +#define GPIOE_PIN5                  5U +#define GPIOE_PIN6                  6U +#define GPIOE_PIN7                  7U +#define GPIOE_PIN8                  8U +#define GPIOE_PIN9                  9U +#define GPIOE_PIN10                 10U +#define GPIOE_PIN11                 11U +#define GPIOE_PIN12                 12U +#define GPIOE_PIN13                 13U +#define GPIOE_PIN14                 14U +#define GPIOE_PIN15                 15U + +#define GPIOF_PIN0                  0U +#define GPIOF_PIN1                  1U +#define GPIOF_PIN2                  2U +#define GPIOF_PIN3                  3U +#define GPIOF_PIN4                  4U +#define GPIOF_PIN5                  5U +#define GPIOF_PIN6                  6U +#define GPIOF_PIN7                  7U +#define GPIOF_PIN8                  8U +#define GPIOF_PIN9                  9U +#define GPIOF_PIN10                 10U +#define GPIOF_PIN11                 11U +#define GPIOF_PIN12                 12U +#define GPIOF_PIN13                 13U +#define GPIOF_PIN14                 14U +#define GPIOF_PIN15                 15U + +/* + * IO lines assignments. + */ + +#define LINE_BOOT0                  PAL_LINE(GPIOB, 8U) +#define LINE_SWCLK                  PAL_LINE(GPIOA, 14U) +#define LINE_SWDIO                  PAL_LINE(GPIOA, 13U) + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n)           (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n)          (1U << ((n) * 2U)) +#define PIN_MODE_ALTERNATE(n)       (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n)          (3U << ((n) * 2U)) +#define PIN_ODR_LOW(n)              (0U << (n)) +#define PIN_ODR_HIGH(n)             (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n)       (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n)      (1U << (n)) +#define PIN_OSPEED_VERYLOW(n)       (0U << ((n) * 2U)) +#define PIN_OSPEED_LOW(n)           (1U << ((n) * 2U)) +#define PIN_OSPEED_MEDIUM(n)        (2U << ((n) * 2U)) +#define PIN_OSPEED_HIGH(n)          (3U << ((n) * 2U)) +#define PIN_PUPDR_FLOATING(n)       (0U << ((n) * 2U)) +#define PIN_PUPDR_PULLUP(n)         (1U << ((n) * 2U)) +#define PIN_PUPDR_PULLDOWN(n)       (2U << ((n) * 2U)) +#define PIN_AFIO_AF(n, v)           ((v) << (((n) % 8U) * 4U)) + +/* + * GPIOA setup: + * + * PA0  - COL5 + * PA1  - COL4 + * PA2  - COL3 + * PA3  - COL2 + * PA4  - COL1 + * PA5  - COL0 + * PA6  - ROW4 + * PA7  - ROW3 + * PA8  - NC + * PA9  - ROW1 + * PA10 - ROW0 + * PA11 - USB_DM + * PA12 - USB_DP + * PA13 - COL15/SWDIO (for now, COL15) + * PA14 - COL14/SWCLK (for now, COL14) + * PA15 - COL13 + */ +#define VAL_GPIOA_MODER             (PIN_MODE_INPUT(GPIOA_PIN0) |           \ +                                     PIN_MODE_INPUT(GPIOA_PIN1) |           \ +                                     PIN_MODE_INPUT(GPIOA_PIN2) |     \ +                                     PIN_MODE_INPUT(GPIOA_PIN3) |         \ +                                     PIN_MODE_INPUT(GPIOA_PIN4) |         \ +                                     PIN_MODE_INPUT(GPIOA_PIN5) |         \ +                                     PIN_MODE_INPUT(GPIOA_PIN6) |         \ +                                     PIN_MODE_INPUT(GPIOA_PIN7) |         \ +                                     PIN_MODE_INPUT(GPIOA_PIN8) |         \ +                                     PIN_MODE_INPUT(GPIOA_PIN9) |         \ +                                     PIN_MODE_INPUT(GPIOA_PIN10) |         \ +                                     PIN_MODE_INPUT(GPIOA_PIN11) |         \ +                                     PIN_MODE_INPUT(GPIOA_PIN12) |         \ +                                     PIN_MODE_INPUT(GPIOA_PIN13) |      \ +                                     PIN_MODE_INPUT(GPIOA_PIN14) |      \ +                                     PIN_MODE_INPUT(GPIOA_PIN15)) +#define VAL_GPIOA_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN1) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN2) |     \ +                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN3) |     \ +                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN4) |     \ +                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN5) |     \ +                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN6) |     \ +                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN7) |     \ +                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN8) |     \ +                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN9) |     \ +                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN10) |     \ +                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN11) |     \ +                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN12) |     \ +                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN13) |      \ +                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN14) |      \ +                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) +#define VAL_GPIOA_OSPEEDR           (PIN_OSPEED_VERYLOW(GPIOA_PIN0) |          \ +                                     PIN_OSPEED_VERYLOW(GPIOA_PIN1) |          \ +                                     PIN_OSPEED_VERYLOW(GPIOA_PIN2) |         \ +                                     PIN_OSPEED_VERYLOW(GPIOA_PIN3) |         \ +                                     PIN_OSPEED_VERYLOW(GPIOA_PIN4) |        \ +                                     PIN_OSPEED_VERYLOW(GPIOA_PIN5) |         \ +                                     PIN_OSPEED_VERYLOW(GPIOA_PIN6) |        \ +                                     PIN_OSPEED_VERYLOW(GPIOA_PIN7) |        \ +                                     PIN_OSPEED_VERYLOW(GPIOA_PIN8) |        \ +                                     PIN_OSPEED_VERYLOW(GPIOA_PIN9) |        \ +                                     PIN_OSPEED_VERYLOW(GPIOA_PIN10) |        \ +                                     PIN_OSPEED_HIGH(GPIOA_PIN11) |        \ +                                     PIN_OSPEED_VERYLOW(GPIOA_PIN12) |        \ +                                     PIN_OSPEED_VERYLOW(GPIOA_PIN13) |         \ +                                     PIN_OSPEED_VERYLOW(GPIOA_PIN14) |         \ +                                     PIN_OSPEED_VERYLOW(GPIOA_PIN15)) +#define VAL_GPIOA_PUPDR             (PIN_PUPDR_PULLUP(GPIOA_PIN0) |         \ +                                     PIN_PUPDR_PULLUP(GPIOA_PIN1) |         \ +                                     PIN_PUPDR_PULLUP(GPIOA_PIN2) |     \ +                                     PIN_PUPDR_PULLUP(GPIOA_PIN3) |       \ +                                     PIN_PUPDR_PULLUP(GPIOA_PIN4) |       \ +                                     PIN_PUPDR_PULLUP(GPIOA_PIN5) |       \ +                                     PIN_PUPDR_PULLUP(GPIOA_PIN6) |       \ +                                     PIN_PUPDR_PULLUP(GPIOA_PIN7) |       \ +                                     PIN_PUPDR_PULLUP(GPIOA_PIN8) |       \ +                                     PIN_PUPDR_PULLUP(GPIOA_PIN9) |       \ +                                     PIN_PUPDR_PULLUP(GPIOA_PIN10) |       \ +                                     PIN_PUPDR_FLOATING(GPIOA_PIN11) |       \ +                                     PIN_PUPDR_FLOATING(GPIOA_PIN12) |       \ +                                     PIN_PUPDR_PULLUP(GPIOA_PIN13) |        \ +                                     PIN_PUPDR_PULLUP(GPIOA_PIN14) |      \ +                                     PIN_PUPDR_PULLUP(GPIOA_PIN15)) +#define VAL_GPIOA_ODR               (PIN_ODR_HIGH(GPIOA_PIN0) |             \ +                                     PIN_ODR_HIGH(GPIOA_PIN1) |             \ +                                     PIN_ODR_HIGH(GPIOA_PIN2) |           \ +                                     PIN_ODR_HIGH(GPIOA_PIN3) |           \ +                                     PIN_ODR_HIGH(GPIOA_PIN4) |           \ +                                     PIN_ODR_HIGH(GPIOA_PIN5) |            \ +                                     PIN_ODR_HIGH(GPIOA_PIN6) |           \ +                                     PIN_ODR_HIGH(GPIOA_PIN7) |           \ +                                     PIN_ODR_HIGH(GPIOA_PIN8) |           \ +                                     PIN_ODR_HIGH(GPIOA_PIN9) |           \ +                                     PIN_ODR_HIGH(GPIOA_PIN10) |           \ +                                     PIN_ODR_HIGH(GPIOA_PIN11) |           \ +                                     PIN_ODR_HIGH(GPIOA_PIN12) |           \ +                                     PIN_ODR_HIGH(GPIOA_PIN13) |            \ +                                     PIN_ODR_HIGH(GPIOA_PIN14) |            \ +                                     PIN_ODR_HIGH(GPIOA_PIN15)) +#define VAL_GPIOA_AFRL              (PIN_AFIO_AF(GPIOA_PIN0, 0U) |          \ +                                     PIN_AFIO_AF(GPIOA_PIN1, 0U) |          \ +                                     PIN_AFIO_AF(GPIOA_PIN2, 0U) |        \ +                                     PIN_AFIO_AF(GPIOA_PIN3, 0U) |        \ +                                     PIN_AFIO_AF(GPIOA_PIN4, 0U) |        \ +                                     PIN_AFIO_AF(GPIOA_PIN5, 0U) |        \ +                                     PIN_AFIO_AF(GPIOA_PIN6, 0U) |        \ +                                     PIN_AFIO_AF(GPIOA_PIN7, 0U)) +#define VAL_GPIOA_AFRH              (PIN_AFIO_AF(GPIOA_PIN8, 0U) |        \ +                                     PIN_AFIO_AF(GPIOA_PIN9, 0U) |        \ +                                     PIN_AFIO_AF(GPIOA_PIN10, 0U) |        \ +                                     PIN_AFIO_AF(GPIOA_PIN11, 0U) |        \ +                                     PIN_AFIO_AF(GPIOA_PIN12, 0U) |        \ +                                     PIN_AFIO_AF(GPIOA_PIN13, 0U) |         \ +                                     PIN_AFIO_AF(GPIOA_PIN14, 0U) |         \ +                                     PIN_AFIO_AF(GPIOA_PIN15, 0U)) + +/* + * GPIOB setup: + * + * PB0  - ROW2 + * PB1  - RGB_D + * PB2  - PIN2                      (input pullup). + * PB3  - COL12 + * PB4  - COL11 + * PB5  - COL10 + * PB6  - COL9 + * PB7  - COL8 + * PB8  - BOOT0 (set as output for STM32F042) + * PB9  - PIN9                      (input pullup). + * PB10 - PIN10                     (input pullup). + * PB11 - PIN11                     (input pullup). + * PB12 - PIN12                     (input pullup). + * PB13 - PIN13                     (input pullup). + * PB14 - PIN14                     (input pullup). + * PB15 - PIN15                     (input pullup). + */ +#define VAL_GPIOB_MODER             (PIN_MODE_INPUT(GPIOB_PIN0) |         \ +                                     PIN_MODE_OUTPUT(GPIOB_PIN1) |         \ +                                     PIN_MODE_INPUT(GPIOB_PIN2) |           \ +                                     PIN_MODE_INPUT(GPIOB_PIN3) |       \ +                                     PIN_MODE_INPUT(GPIOB_PIN4) |        \ +                                     PIN_MODE_INPUT(GPIOB_PIN5) |        \ +                                     PIN_MODE_INPUT(GPIOB_PIN6) |         \ +                                     PIN_MODE_INPUT(GPIOB_PIN7) |         \ +                                     PIN_MODE_OUTPUT(GPIOB_PIN8) |           \ +                                     PIN_MODE_INPUT(GPIOB_PIN9) |           \ +                                     PIN_MODE_INPUT(GPIOB_PIN10) |          \ +                                     PIN_MODE_INPUT(GPIOB_PIN11) |          \ +                                     PIN_MODE_INPUT(GPIOB_PIN12) |          \ +                                     PIN_MODE_INPUT(GPIOB_PIN13) |          \ +                                     PIN_MODE_INPUT(GPIOB_PIN14) |          \ +                                     PIN_MODE_INPUT(GPIOB_PIN15)) +#define VAL_GPIOB_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) |     \ +                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN1) |     \ +                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN2) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN3) |    \ +                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN4) |    \ +                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN5) |    \ +                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN6) |     \ +                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN7) |     \ +                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN8) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN9) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN10) |      \ +                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN11) |      \ +                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN12) |      \ +                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN13) |      \ +                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN14) |      \ +                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) +#define VAL_GPIOB_OSPEEDR           (PIN_OSPEED_VERYLOW(GPIOB_PIN0) |        \ +                                     PIN_OSPEED_HIGH(GPIOB_PIN1) |        \ +                                     PIN_OSPEED_HIGH(GPIOB_PIN2) |          \ +                                     PIN_OSPEED_VERYLOW(GPIOB_PIN3) |       \ +                                     PIN_OSPEED_VERYLOW(GPIOB_PIN4) |       \ +                                     PIN_OSPEED_VERYLOW(GPIOB_PIN5) |       \ +                                     PIN_OSPEED_VERYLOW(GPIOB_PIN6) |        \ +                                     PIN_OSPEED_VERYLOW(GPIOB_PIN7) |        \ +                                     PIN_OSPEED_VERYLOW(GPIOB_PIN8) |          \ +                                     PIN_OSPEED_HIGH(GPIOB_PIN9) |          \ +                                     PIN_OSPEED_HIGH(GPIOB_PIN10) |         \ +                                     PIN_OSPEED_HIGH(GPIOB_PIN11) |         \ +                                     PIN_OSPEED_HIGH(GPIOB_PIN12) |         \ +                                     PIN_OSPEED_HIGH(GPIOB_PIN13) |         \ +                                     PIN_OSPEED_HIGH(GPIOB_PIN14) |         \ +                                     PIN_OSPEED_HIGH(GPIOB_PIN15)) +#define VAL_GPIOB_PUPDR             (PIN_PUPDR_PULLUP(GPIOB_PIN0) |       \ +                                     PIN_PUPDR_FLOATING(GPIOB_PIN1) |       \ +                                     PIN_PUPDR_PULLUP(GPIOB_PIN2) |         \ +                                     PIN_PUPDR_PULLUP(GPIOB_PIN3) |    \ +                                     PIN_PUPDR_PULLUP(GPIOB_PIN4) |      \ +                                     PIN_PUPDR_PULLUP(GPIOB_PIN5) |      \ +                                     PIN_PUPDR_PULLUP(GPIOB_PIN6) |       \ +                                     PIN_PUPDR_PULLUP(GPIOB_PIN7) |       \ +                                     PIN_PUPDR_PULLDOWN(GPIOB_PIN8) |         \ +                                     PIN_PUPDR_PULLUP(GPIOB_PIN9) |         \ +                                     PIN_PUPDR_PULLUP(GPIOB_PIN10) |        \ +                                     PIN_PUPDR_PULLUP(GPIOB_PIN11) |        \ +                                     PIN_PUPDR_PULLUP(GPIOB_PIN12) |        \ +                                     PIN_PUPDR_PULLUP(GPIOB_PIN13) |        \ +                                     PIN_PUPDR_PULLUP(GPIOB_PIN14) |        \ +                                     PIN_PUPDR_PULLUP(GPIOB_PIN15)) +#define VAL_GPIOB_ODR               (PIN_ODR_HIGH(GPIOB_PIN0) |           \ +                                     PIN_ODR_HIGH(GPIOB_PIN1) |           \ +                                     PIN_ODR_HIGH(GPIOB_PIN2) |             \ +                                     PIN_ODR_HIGH(GPIOB_PIN3) |           \ +                                     PIN_ODR_HIGH(GPIOB_PIN4) |          \ +                                     PIN_ODR_HIGH(GPIOB_PIN5) |          \ +                                     PIN_ODR_HIGH(GPIOB_PIN6) |           \ +                                     PIN_ODR_HIGH(GPIOB_PIN7) |           \ +                                     PIN_ODR_HIGH(GPIOB_PIN8) |             \ +                                     PIN_ODR_HIGH(GPIOB_PIN9) |             \ +                                     PIN_ODR_HIGH(GPIOB_PIN10) |            \ +                                     PIN_ODR_HIGH(GPIOB_PIN11) |            \ +                                     PIN_ODR_HIGH(GPIOB_PIN12) |            \ +                                     PIN_ODR_HIGH(GPIOB_PIN13) |            \ +                                     PIN_ODR_HIGH(GPIOB_PIN14) |            \ +                                     PIN_ODR_HIGH(GPIOB_PIN15)) +#define VAL_GPIOB_AFRL              (PIN_AFIO_AF(GPIOB_PIN0, 0U) |        \ +                                     PIN_AFIO_AF(GPIOB_PIN1, 0U) |        \ +                                     PIN_AFIO_AF(GPIOB_PIN2, 0U) |          \ +                                     PIN_AFIO_AF(GPIOB_PIN3, 0U) |       \ +                                     PIN_AFIO_AF(GPIOB_PIN4, 0U) |       \ +                                     PIN_AFIO_AF(GPIOB_PIN5, 0U) |       \ +                                     PIN_AFIO_AF(GPIOB_PIN6, 0U) |        \ +                                     PIN_AFIO_AF(GPIOB_PIN7, 0U)) +#define VAL_GPIOB_AFRH              (PIN_AFIO_AF(GPIOB_PIN8, 0U) |          \ +                                     PIN_AFIO_AF(GPIOB_PIN9, 0U) |          \ +                                     PIN_AFIO_AF(GPIOB_PIN10, 0U) |         \ +                                     PIN_AFIO_AF(GPIOB_PIN11, 0U) |         \ +                                     PIN_AFIO_AF(GPIOB_PIN12, 0U) |         \ +                                     PIN_AFIO_AF(GPIOB_PIN13, 0U) |         \ +                                     PIN_AFIO_AF(GPIOB_PIN14, 0U) |         \ +                                     PIN_AFIO_AF(GPIOB_PIN15, 0U)) + +/* + * GPIOC setup: + * + * PC0  - PIN0                      (input pullup). + * PC1  - PIN1                      (input pullup). + * PC2  - PIN2                      (input pullup). + * PC3  - PIN3                      (input pullup). + * PC4  - PIN4                      (input pullup). + * PC5  - PIN5                      (input pullup). + * PC6  - PIN6                      (input pullup). + * PC7  - PIN7                      (input pullup). + * PC8  - PIN8                      (input pullup). + * PC9  - PIN9                      (input pullup). + * PC10 - PIN10                     (input pullup). + * PC11 - PIN11                     (input pullup). + * PC12 - PIN12                     (input pullup). + * PC13 - PIN13                     (input pullup). + * PC14 - PIN14                     (input pullup). + * PC15 - PIN15                     (input pullup). + */ +#define VAL_GPIOC_MODER             (PIN_MODE_INPUT(GPIOC_PIN0) |           \ +                                     PIN_MODE_INPUT(GPIOC_PIN1) |           \ +                                     PIN_MODE_INPUT(GPIOC_PIN2) |           \ +                                     PIN_MODE_INPUT(GPIOC_PIN3) |           \ +                                     PIN_MODE_INPUT(GPIOC_PIN4) |           \ +                                     PIN_MODE_INPUT(GPIOC_PIN5) |           \ +                                     PIN_MODE_INPUT(GPIOC_PIN6) |           \ +                                     PIN_MODE_INPUT(GPIOC_PIN7) |           \ +                                     PIN_MODE_INPUT(GPIOC_PIN8) |           \ +                                     PIN_MODE_INPUT(GPIOC_PIN9) |           \ +                                     PIN_MODE_INPUT(GPIOC_PIN10) |          \ +                                     PIN_MODE_INPUT(GPIOC_PIN11) |          \ +                                     PIN_MODE_INPUT(GPIOC_PIN12) |          \ +                                     PIN_MODE_INPUT(GPIOC_PIN13) |          \ +                                     PIN_MODE_INPUT(GPIOC_PIN14) |          \ +                                     PIN_MODE_INPUT(GPIOC_PIN15)) +#define VAL_GPIOC_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN1) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN2) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN3) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN4) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN5) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN6) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN7) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN8) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN9) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN10) |      \ +                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN11) |      \ +                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN12) |      \ +                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN13) |      \ +                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN14) |      \ +                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN15)) +#define VAL_GPIOC_OSPEEDR           (PIN_OSPEED_HIGH(GPIOC_PIN0) |          \ +                                     PIN_OSPEED_HIGH(GPIOC_PIN1) |          \ +                                     PIN_OSPEED_HIGH(GPIOC_PIN2) |          \ +                                     PIN_OSPEED_HIGH(GPIOC_PIN3) |          \ +                                     PIN_OSPEED_HIGH(GPIOC_PIN4) |          \ +                                     PIN_OSPEED_HIGH(GPIOC_PIN5) |          \ +                                     PIN_OSPEED_HIGH(GPIOC_PIN6) |          \ +                                     PIN_OSPEED_HIGH(GPIOC_PIN7) |          \ +                                     PIN_OSPEED_HIGH(GPIOC_PIN8) |          \ +                                     PIN_OSPEED_HIGH(GPIOC_PIN9) |          \ +                                     PIN_OSPEED_HIGH(GPIOC_PIN10) |         \ +                                     PIN_OSPEED_HIGH(GPIOC_PIN11) |         \ +                                     PIN_OSPEED_HIGH(GPIOC_PIN12) |         \ +                                     PIN_OSPEED_HIGH(GPIOC_PIN13) |         \ +                                     PIN_OSPEED_HIGH(GPIOC_PIN14) |         \ +                                     PIN_OSPEED_HIGH(GPIOC_PIN15)) +#define VAL_GPIOC_PUPDR             (PIN_PUPDR_PULLUP(GPIOC_PIN0) |         \ +                                     PIN_PUPDR_PULLUP(GPIOC_PIN1) |         \ +                                     PIN_PUPDR_PULLUP(GPIOC_PIN2) |         \ +                                     PIN_PUPDR_PULLUP(GPIOC_PIN3) |         \ +                                     PIN_PUPDR_PULLUP(GPIOC_PIN4) |         \ +                                     PIN_PUPDR_PULLUP(GPIOC_PIN5) |         \ +                                     PIN_PUPDR_PULLUP(GPIOC_PIN6) |         \ +                                     PIN_PUPDR_PULLUP(GPIOC_PIN7) |         \ +                                     PIN_PUPDR_PULLUP(GPIOC_PIN8) |         \ +                                     PIN_PUPDR_PULLUP(GPIOC_PIN9) |         \ +                                     PIN_PUPDR_PULLUP(GPIOC_PIN10) |        \ +                                     PIN_PUPDR_PULLUP(GPIOC_PIN11) |        \ +                                     PIN_PUPDR_PULLUP(GPIOC_PIN12) |        \ +                                     PIN_PUPDR_PULLUP(GPIOC_PIN13) |        \ +                                     PIN_PUPDR_PULLUP(GPIOC_PIN14) |        \ +                                     PIN_PUPDR_PULLUP(GPIOC_PIN15)) +#define VAL_GPIOC_ODR               (PIN_ODR_HIGH(GPIOC_PIN0) |             \ +                                     PIN_ODR_HIGH(GPIOC_PIN1) |             \ +                                     PIN_ODR_HIGH(GPIOC_PIN2) |             \ +                                     PIN_ODR_HIGH(GPIOC_PIN3) |             \ +                                     PIN_ODR_HIGH(GPIOC_PIN4) |             \ +                                     PIN_ODR_HIGH(GPIOC_PIN5) |             \ +                                     PIN_ODR_HIGH(GPIOC_PIN6) |             \ +                                     PIN_ODR_HIGH(GPIOC_PIN7) |             \ +                                     PIN_ODR_HIGH(GPIOC_PIN8) |             \ +                                     PIN_ODR_HIGH(GPIOC_PIN9) |             \ +                                     PIN_ODR_HIGH(GPIOC_PIN10) |            \ +                                     PIN_ODR_HIGH(GPIOC_PIN11) |            \ +                                     PIN_ODR_HIGH(GPIOC_PIN12) |            \ +                                     PIN_ODR_HIGH(GPIOC_PIN13) |            \ +                                     PIN_ODR_HIGH(GPIOC_PIN14) |            \ +                                     PIN_ODR_HIGH(GPIOC_PIN15)) +#define VAL_GPIOC_AFRL              (PIN_AFIO_AF(GPIOC_PIN0, 0U) |          \ +                                     PIN_AFIO_AF(GPIOC_PIN1, 0U) |          \ +                                     PIN_AFIO_AF(GPIOC_PIN2, 0U) |          \ +                                     PIN_AFIO_AF(GPIOC_PIN3, 0U) |          \ +                                     PIN_AFIO_AF(GPIOC_PIN4, 0U) |          \ +                                     PIN_AFIO_AF(GPIOC_PIN5, 0U) |          \ +                                     PIN_AFIO_AF(GPIOC_PIN6, 0U) |          \ +                                     PIN_AFIO_AF(GPIOC_PIN7, 0U)) +#define VAL_GPIOC_AFRH              (PIN_AFIO_AF(GPIOC_PIN8, 0U) |          \ +                                     PIN_AFIO_AF(GPIOC_PIN9, 0U) |          \ +                                     PIN_AFIO_AF(GPIOC_PIN10, 0U) |         \ +                                     PIN_AFIO_AF(GPIOC_PIN11, 0U) |         \ +                                     PIN_AFIO_AF(GPIOC_PIN12, 0U) |         \ +                                     PIN_AFIO_AF(GPIOC_PIN13, 0U) |         \ +                                     PIN_AFIO_AF(GPIOC_PIN14, 0U) |         \ +                                     PIN_AFIO_AF(GPIOC_PIN15, 0U)) + +/* + * GPIOD setup: + * + * PD0  - PIN0                      (input pullup). + * PD1  - PIN1                      (input pullup). + * PD2  - PIN2                      (input pullup). + * PD3  - PIN3                      (input pullup). + * PD4  - PIN4                      (input pullup). + * PD5  - PIN5                      (input pullup). + * PD6  - PIN6                      (input pullup). + * PD7  - PIN7                      (input pullup). + * PD8  - PIN8                      (input pullup). + * PD9  - PIN9                      (input pullup). + * PD10 - PIN10                     (input pullup). + * PD11 - PIN11                     (input pullup). + * PD12 - PIN12                     (input pullup). + * PD13 - PIN13                     (input pullup). + * PD14 - PIN14                     (input pullup). + * PD15 - PIN15                     (input pullup). + */ +#define VAL_GPIOD_MODER             (PIN_MODE_INPUT(GPIOD_PIN0) |           \ +                                     PIN_MODE_INPUT(GPIOD_PIN1) |           \ +                                     PIN_MODE_INPUT(GPIOD_PIN2) |           \ +                                     PIN_MODE_INPUT(GPIOD_PIN3) |           \ +                                     PIN_MODE_INPUT(GPIOD_PIN4) |           \ +                                     PIN_MODE_INPUT(GPIOD_PIN5) |           \ +                                     PIN_MODE_INPUT(GPIOD_PIN6) |           \ +                                     PIN_MODE_INPUT(GPIOD_PIN7) |           \ +                                     PIN_MODE_INPUT(GPIOD_PIN8) |           \ +                                     PIN_MODE_INPUT(GPIOD_PIN9) |           \ +                                     PIN_MODE_INPUT(GPIOD_PIN10) |          \ +                                     PIN_MODE_INPUT(GPIOD_PIN11) |          \ +                                     PIN_MODE_INPUT(GPIOD_PIN12) |          \ +                                     PIN_MODE_INPUT(GPIOD_PIN13) |          \ +                                     PIN_MODE_INPUT(GPIOD_PIN14) |          \ +                                     PIN_MODE_INPUT(GPIOD_PIN15)) +#define VAL_GPIOD_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN1) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN2) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN3) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN4) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN5) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN6) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN7) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN8) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN9) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN10) |      \ +                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN11) |      \ +                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN12) |      \ +                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN13) |      \ +                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN14) |      \ +                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) +#define VAL_GPIOD_OSPEEDR           (PIN_OSPEED_HIGH(GPIOD_PIN0) |          \ +                                     PIN_OSPEED_HIGH(GPIOD_PIN1) |          \ +                                     PIN_OSPEED_HIGH(GPIOD_PIN2) |          \ +                                     PIN_OSPEED_HIGH(GPIOD_PIN3) |          \ +                                     PIN_OSPEED_HIGH(GPIOD_PIN4) |          \ +                                     PIN_OSPEED_HIGH(GPIOD_PIN5) |          \ +                                     PIN_OSPEED_HIGH(GPIOD_PIN6) |          \ +                                     PIN_OSPEED_HIGH(GPIOD_PIN7) |          \ +                                     PIN_OSPEED_HIGH(GPIOD_PIN8) |          \ +                                     PIN_OSPEED_HIGH(GPIOD_PIN9) |          \ +                                     PIN_OSPEED_HIGH(GPIOD_PIN10) |         \ +                                     PIN_OSPEED_HIGH(GPIOD_PIN11) |         \ +                                     PIN_OSPEED_HIGH(GPIOD_PIN12) |         \ +                                     PIN_OSPEED_HIGH(GPIOD_PIN13) |         \ +                                     PIN_OSPEED_HIGH(GPIOD_PIN14) |         \ +                                     PIN_OSPEED_HIGH(GPIOD_PIN15)) +#define VAL_GPIOD_PUPDR             (PIN_PUPDR_PULLUP(GPIOD_PIN0) |         \ +                                     PIN_PUPDR_PULLUP(GPIOD_PIN1) |         \ +                                     PIN_PUPDR_PULLUP(GPIOD_PIN2) |         \ +                                     PIN_PUPDR_PULLUP(GPIOD_PIN3) |         \ +                                     PIN_PUPDR_PULLUP(GPIOD_PIN4) |         \ +                                     PIN_PUPDR_PULLUP(GPIOD_PIN5) |         \ +                                     PIN_PUPDR_PULLUP(GPIOD_PIN6) |         \ +                                     PIN_PUPDR_PULLUP(GPIOD_PIN7) |         \ +                                     PIN_PUPDR_PULLUP(GPIOD_PIN8) |         \ +                                     PIN_PUPDR_PULLUP(GPIOD_PIN9) |         \ +                                     PIN_PUPDR_PULLUP(GPIOD_PIN10) |        \ +                                     PIN_PUPDR_PULLUP(GPIOD_PIN11) |        \ +                                     PIN_PUPDR_PULLUP(GPIOD_PIN12) |        \ +                                     PIN_PUPDR_PULLUP(GPIOD_PIN13) |        \ +                                     PIN_PUPDR_PULLUP(GPIOD_PIN14) |        \ +                                     PIN_PUPDR_PULLUP(GPIOD_PIN15)) +#define VAL_GPIOD_ODR               (PIN_ODR_HIGH(GPIOD_PIN0) |             \ +                                     PIN_ODR_HIGH(GPIOD_PIN1) |             \ +                                     PIN_ODR_HIGH(GPIOD_PIN2) |             \ +                                     PIN_ODR_HIGH(GPIOD_PIN3) |             \ +                                     PIN_ODR_HIGH(GPIOD_PIN4) |             \ +                                     PIN_ODR_HIGH(GPIOD_PIN5) |             \ +                                     PIN_ODR_HIGH(GPIOD_PIN6) |             \ +                                     PIN_ODR_HIGH(GPIOD_PIN7) |             \ +                                     PIN_ODR_HIGH(GPIOD_PIN8) |             \ +                                     PIN_ODR_HIGH(GPIOD_PIN9) |             \ +                                     PIN_ODR_HIGH(GPIOD_PIN10) |            \ +                                     PIN_ODR_HIGH(GPIOD_PIN11) |            \ +                                     PIN_ODR_HIGH(GPIOD_PIN12) |            \ +                                     PIN_ODR_HIGH(GPIOD_PIN13) |            \ +                                     PIN_ODR_HIGH(GPIOD_PIN14) |            \ +                                     PIN_ODR_HIGH(GPIOD_PIN15)) +#define VAL_GPIOD_AFRL              (PIN_AFIO_AF(GPIOD_PIN0, 0U) |          \ +                                     PIN_AFIO_AF(GPIOD_PIN1, 0U) |          \ +                                     PIN_AFIO_AF(GPIOD_PIN2, 0U) |          \ +                                     PIN_AFIO_AF(GPIOD_PIN3, 0U) |          \ +                                     PIN_AFIO_AF(GPIOD_PIN4, 0U) |          \ +                                     PIN_AFIO_AF(GPIOD_PIN5, 0U) |          \ +                                     PIN_AFIO_AF(GPIOD_PIN6, 0U) |          \ +                                     PIN_AFIO_AF(GPIOD_PIN7, 0U)) +#define VAL_GPIOD_AFRH              (PIN_AFIO_AF(GPIOD_PIN8, 0U) |          \ +                                     PIN_AFIO_AF(GPIOD_PIN9, 0U) |          \ +                                     PIN_AFIO_AF(GPIOD_PIN10, 0U) |         \ +                                     PIN_AFIO_AF(GPIOD_PIN11, 0U) |         \ +                                     PIN_AFIO_AF(GPIOD_PIN12, 0U) |         \ +                                     PIN_AFIO_AF(GPIOD_PIN13, 0U) |         \ +                                     PIN_AFIO_AF(GPIOD_PIN14, 0U) |         \ +                                     PIN_AFIO_AF(GPIOD_PIN15, 0U)) + +/* + * GPIOE setup: + * + * PE0  - PIN0                      (input pullup). + * PE1  - PIN1                      (input pullup). + * PE2  - PIN2                      (input pullup). + * PE3  - PIN3                      (input pullup). + * PE4  - PIN4                      (input pullup). + * PE5  - PIN5                      (input pullup). + * PE6  - PIN6                      (input pullup). + * PE7  - PIN7                      (input pullup). + * PE8  - PIN8                      (input pullup). + * PE9  - PIN9                      (input pullup). + * PE10 - PIN10                     (input pullup). + * PE11 - PIN11                     (input pullup). + * PE12 - PIN12                     (input pullup). + * PE13 - PIN13                     (input pullup). + * PE14 - PIN14                     (input pullup). + * PE15 - PIN15                     (input pullup). + */ +#define VAL_GPIOE_MODER             (PIN_MODE_INPUT(GPIOE_PIN0) |           \ +                                     PIN_MODE_INPUT(GPIOE_PIN1) |           \ +                                     PIN_MODE_INPUT(GPIOE_PIN2) |           \ +                                     PIN_MODE_INPUT(GPIOE_PIN3) |           \ +                                     PIN_MODE_INPUT(GPIOE_PIN4) |           \ +                                     PIN_MODE_INPUT(GPIOE_PIN5) |           \ +                                     PIN_MODE_INPUT(GPIOE_PIN6) |           \ +                                     PIN_MODE_INPUT(GPIOE_PIN7) |           \ +                                     PIN_MODE_INPUT(GPIOE_PIN8) |           \ +                                     PIN_MODE_INPUT(GPIOE_PIN9) |           \ +                                     PIN_MODE_INPUT(GPIOE_PIN10) |          \ +                                     PIN_MODE_INPUT(GPIOE_PIN11) |          \ +                                     PIN_MODE_INPUT(GPIOE_PIN12) |          \ +                                     PIN_MODE_INPUT(GPIOE_PIN13) |          \ +                                     PIN_MODE_INPUT(GPIOE_PIN14) |          \ +                                     PIN_MODE_INPUT(GPIOE_PIN15)) +#define VAL_GPIOE_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN1) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN2) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN3) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN4) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN5) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN6) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN7) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN8) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN9) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN10) |      \ +                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN11) |      \ +                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN12) |      \ +                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN13) |      \ +                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN14) |      \ +                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) +#define VAL_GPIOE_OSPEEDR           (PIN_OSPEED_HIGH(GPIOE_PIN0) |          \ +                                     PIN_OSPEED_HIGH(GPIOE_PIN1) |          \ +                                     PIN_OSPEED_HIGH(GPIOE_PIN2) |          \ +                                     PIN_OSPEED_HIGH(GPIOE_PIN3) |          \ +                                     PIN_OSPEED_HIGH(GPIOE_PIN4) |          \ +                                     PIN_OSPEED_HIGH(GPIOE_PIN5) |          \ +                                     PIN_OSPEED_HIGH(GPIOE_PIN6) |          \ +                                     PIN_OSPEED_HIGH(GPIOE_PIN7) |          \ +                                     PIN_OSPEED_HIGH(GPIOE_PIN8) |          \ +                                     PIN_OSPEED_HIGH(GPIOE_PIN9) |          \ +                                     PIN_OSPEED_HIGH(GPIOE_PIN10) |         \ +                                     PIN_OSPEED_HIGH(GPIOE_PIN11) |         \ +                                     PIN_OSPEED_HIGH(GPIOE_PIN12) |         \ +                                     PIN_OSPEED_HIGH(GPIOE_PIN13) |         \ +                                     PIN_OSPEED_HIGH(GPIOE_PIN14) |         \ +                                     PIN_OSPEED_HIGH(GPIOE_PIN15)) +#define VAL_GPIOE_PUPDR             (PIN_PUPDR_PULLUP(GPIOE_PIN0) |         \ +                                     PIN_PUPDR_PULLUP(GPIOE_PIN1) |         \ +                                     PIN_PUPDR_PULLUP(GPIOE_PIN2) |         \ +                                     PIN_PUPDR_PULLUP(GPIOE_PIN3) |         \ +                                     PIN_PUPDR_PULLUP(GPIOE_PIN4) |         \ +                                     PIN_PUPDR_PULLUP(GPIOE_PIN5) |         \ +                                     PIN_PUPDR_PULLUP(GPIOE_PIN6) |         \ +                                     PIN_PUPDR_PULLUP(GPIOE_PIN7) |         \ +                                     PIN_PUPDR_PULLUP(GPIOE_PIN8) |         \ +                                     PIN_PUPDR_PULLUP(GPIOE_PIN9) |         \ +                                     PIN_PUPDR_PULLUP(GPIOE_PIN10) |        \ +                                     PIN_PUPDR_PULLUP(GPIOE_PIN11) |        \ +                                     PIN_PUPDR_PULLUP(GPIOE_PIN12) |        \ +                                     PIN_PUPDR_PULLUP(GPIOE_PIN13) |        \ +                                     PIN_PUPDR_PULLUP(GPIOE_PIN14) |        \ +                                     PIN_PUPDR_PULLUP(GPIOE_PIN15)) +#define VAL_GPIOE_ODR               (PIN_ODR_HIGH(GPIOE_PIN0) |             \ +                                     PIN_ODR_HIGH(GPIOE_PIN1) |             \ +                                     PIN_ODR_HIGH(GPIOE_PIN2) |             \ +                                     PIN_ODR_HIGH(GPIOE_PIN3) |             \ +                                     PIN_ODR_HIGH(GPIOE_PIN4) |             \ +                                     PIN_ODR_HIGH(GPIOE_PIN5) |             \ +                                     PIN_ODR_HIGH(GPIOE_PIN6) |             \ +                                     PIN_ODR_HIGH(GPIOE_PIN7) |             \ +                                     PIN_ODR_HIGH(GPIOE_PIN8) |             \ +                                     PIN_ODR_HIGH(GPIOE_PIN9) |             \ +                                     PIN_ODR_HIGH(GPIOE_PIN10) |            \ +                                     PIN_ODR_HIGH(GPIOE_PIN11) |            \ +                                     PIN_ODR_HIGH(GPIOE_PIN12) |            \ +                                     PIN_ODR_HIGH(GPIOE_PIN13) |            \ +                                     PIN_ODR_HIGH(GPIOE_PIN14) |            \ +                                     PIN_ODR_HIGH(GPIOE_PIN15)) +#define VAL_GPIOE_AFRL              (PIN_AFIO_AF(GPIOE_PIN0, 0U) |          \ +                                     PIN_AFIO_AF(GPIOE_PIN1, 0U) |          \ +                                     PIN_AFIO_AF(GPIOE_PIN2, 0U) |          \ +                                     PIN_AFIO_AF(GPIOE_PIN3, 0U) |          \ +                                     PIN_AFIO_AF(GPIOE_PIN4, 0U) |          \ +                                     PIN_AFIO_AF(GPIOE_PIN5, 0U) |          \ +                                     PIN_AFIO_AF(GPIOE_PIN6, 0U) |          \ +                                     PIN_AFIO_AF(GPIOE_PIN7, 0U)) +#define VAL_GPIOE_AFRH              (PIN_AFIO_AF(GPIOE_PIN8, 0U) |          \ +                                     PIN_AFIO_AF(GPIOE_PIN9, 0U) |          \ +                                     PIN_AFIO_AF(GPIOE_PIN10, 0U) |         \ +                                     PIN_AFIO_AF(GPIOE_PIN11, 0U) |         \ +                                     PIN_AFIO_AF(GPIOE_PIN12, 0U) |         \ +                                     PIN_AFIO_AF(GPIOE_PIN13, 0U) |         \ +                                     PIN_AFIO_AF(GPIOE_PIN14, 0U) |         \ +                                     PIN_AFIO_AF(GPIOE_PIN15, 0U)) + +/* + * GPIOF setup: + * + * PF0  - COL7 + * PF1  - COL6 + * PF2  - PIN2                      (input pullup). + * PF3  - PIN3                      (input pullup). + * PF4  - PIN4                      (input pullup). + * PF5  - PIN5                      (input pullup). + * PF6  - PIN6                      (input pullup). + * PF7  - PIN7                      (input pullup). + * PF8  - PIN8                      (input pullup). + * PF9  - PIN9                      (input pullup). + * PF10 - PIN10                     (input pullup). + * PF11 - PIN11                     (input pullup). + * PF12 - PIN12                     (input pullup). + * PF13 - PIN13                     (input pullup). + * PF14 - PIN14                     (input pullup). + * PF15 - PIN15                     (input pullup). + */ +#define VAL_GPIOF_MODER             (PIN_MODE_INPUT(GPIOF_PIN0) |         \ +                                     PIN_MODE_INPUT(GPIOF_PIN1) |         \ +                                     PIN_MODE_INPUT(GPIOF_PIN2) |           \ +                                     PIN_MODE_INPUT(GPIOF_PIN3) |           \ +                                     PIN_MODE_INPUT(GPIOF_PIN4) |           \ +                                     PIN_MODE_INPUT(GPIOF_PIN5) |           \ +                                     PIN_MODE_INPUT(GPIOF_PIN6) |           \ +                                     PIN_MODE_INPUT(GPIOF_PIN7) |           \ +                                     PIN_MODE_INPUT(GPIOF_PIN8) |           \ +                                     PIN_MODE_INPUT(GPIOF_PIN9) |           \ +                                     PIN_MODE_INPUT(GPIOF_PIN10) |          \ +                                     PIN_MODE_INPUT(GPIOF_PIN11) |          \ +                                     PIN_MODE_INPUT(GPIOF_PIN12) |          \ +                                     PIN_MODE_INPUT(GPIOF_PIN13) |          \ +                                     PIN_MODE_INPUT(GPIOF_PIN14) |          \ +                                     PIN_MODE_INPUT(GPIOF_PIN15)) +#define VAL_GPIOF_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) |     \ +                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN1) |     \ +                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN2) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN3) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN4) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN5) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN6) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN7) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN8) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN9) |       \ +                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN10) |      \ +                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN11) |      \ +                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN12) |      \ +                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN13) |      \ +                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN14) |      \ +                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) +#define VAL_GPIOF_OSPEEDR           (PIN_OSPEED_VERYLOW(GPIOF_PIN0) |        \ +                                     PIN_OSPEED_VERYLOW(GPIOF_PIN1) |        \ +                                     PIN_OSPEED_HIGH(GPIOF_PIN2) |          \ +                                     PIN_OSPEED_HIGH(GPIOF_PIN3) |          \ +                                     PIN_OSPEED_HIGH(GPIOF_PIN4) |          \ +                                     PIN_OSPEED_HIGH(GPIOF_PIN5) |          \ +                                     PIN_OSPEED_HIGH(GPIOF_PIN6) |          \ +                                     PIN_OSPEED_HIGH(GPIOF_PIN7) |          \ +                                     PIN_OSPEED_HIGH(GPIOF_PIN8) |          \ +                                     PIN_OSPEED_HIGH(GPIOF_PIN9) |          \ +                                     PIN_OSPEED_HIGH(GPIOF_PIN10) |         \ +                                     PIN_OSPEED_HIGH(GPIOF_PIN11) |         \ +                                     PIN_OSPEED_HIGH(GPIOF_PIN12) |         \ +                                     PIN_OSPEED_HIGH(GPIOF_PIN13) |         \ +                                     PIN_OSPEED_HIGH(GPIOF_PIN14) |         \ +                                     PIN_OSPEED_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_PUPDR             (PIN_PUPDR_PULLUP(GPIOF_PIN0) |       \ +                                     PIN_PUPDR_PULLUP(GPIOF_PIN1) |       \ +                                     PIN_PUPDR_PULLUP(GPIOF_PIN2) |         \ +                                     PIN_PUPDR_PULLUP(GPIOF_PIN3) |         \ +                                     PIN_PUPDR_PULLUP(GPIOF_PIN4) |         \ +                                     PIN_PUPDR_PULLUP(GPIOF_PIN5) |         \ +                                     PIN_PUPDR_PULLUP(GPIOF_PIN6) |         \ +                                     PIN_PUPDR_PULLUP(GPIOF_PIN7) |         \ +                                     PIN_PUPDR_PULLUP(GPIOF_PIN8) |         \ +                                     PIN_PUPDR_PULLUP(GPIOF_PIN9) |         \ +                                     PIN_PUPDR_PULLUP(GPIOF_PIN10) |        \ +                                     PIN_PUPDR_PULLUP(GPIOF_PIN11) |        \ +                                     PIN_PUPDR_PULLUP(GPIOF_PIN12) |        \ +                                     PIN_PUPDR_PULLUP(GPIOF_PIN13) |        \ +                                     PIN_PUPDR_PULLUP(GPIOF_PIN14) |        \ +                                     PIN_PUPDR_PULLUP(GPIOF_PIN15)) +#define VAL_GPIOF_ODR               (PIN_ODR_HIGH(GPIOF_PIN0) |           \ +                                     PIN_ODR_HIGH(GPIOF_PIN1) |           \ +                                     PIN_ODR_HIGH(GPIOF_PIN2) |             \ +                                     PIN_ODR_HIGH(GPIOF_PIN3) |             \ +                                     PIN_ODR_HIGH(GPIOF_PIN4) |             \ +                                     PIN_ODR_HIGH(GPIOF_PIN5) |             \ +                                     PIN_ODR_HIGH(GPIOF_PIN6) |             \ +                                     PIN_ODR_HIGH(GPIOF_PIN7) |             \ +                                     PIN_ODR_HIGH(GPIOF_PIN8) |             \ +                                     PIN_ODR_HIGH(GPIOF_PIN9) |             \ +                                     PIN_ODR_HIGH(GPIOF_PIN10) |            \ +                                     PIN_ODR_HIGH(GPIOF_PIN11) |            \ +                                     PIN_ODR_HIGH(GPIOF_PIN12) |            \ +                                     PIN_ODR_HIGH(GPIOF_PIN13) |            \ +                                     PIN_ODR_HIGH(GPIOF_PIN14) |            \ +                                     PIN_ODR_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_AFRL              (PIN_AFIO_AF(GPIOF_PIN0, 0U) |        \ +                                     PIN_AFIO_AF(GPIOF_PIN1, 0U) |        \ +                                     PIN_AFIO_AF(GPIOF_PIN2, 0U) |          \ +                                     PIN_AFIO_AF(GPIOF_PIN3, 0U) |          \ +                                     PIN_AFIO_AF(GPIOF_PIN4, 0U) |          \ +                                     PIN_AFIO_AF(GPIOF_PIN5, 0U) |          \ +                                     PIN_AFIO_AF(GPIOF_PIN6, 0U) |          \ +                                     PIN_AFIO_AF(GPIOF_PIN7, 0U)) +#define VAL_GPIOF_AFRH              (PIN_AFIO_AF(GPIOF_PIN8, 0U) |          \ +                                     PIN_AFIO_AF(GPIOF_PIN9, 0U) |          \ +                                     PIN_AFIO_AF(GPIOF_PIN10, 0U) |         \ +                                     PIN_AFIO_AF(GPIOF_PIN11, 0U) |         \ +                                     PIN_AFIO_AF(GPIOF_PIN12, 0U) |         \ +                                     PIN_AFIO_AF(GPIOF_PIN13, 0U) |         \ +                                     PIN_AFIO_AF(GPIOF_PIN14, 0U) |         \ +                                     PIN_AFIO_AF(GPIOF_PIN15, 0U)) + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif +  void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H */ diff --git a/platforms/chibios/GENERIC_STM32_F042X6/board/board.mk b/platforms/chibios/GENERIC_STM32_F042X6/board/board.mk new file mode 100644 index 0000000000..842e335905 --- /dev/null +++ b/platforms/chibios/GENERIC_STM32_F042X6/board/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = $(BOARD_PATH)/board/board.c + +# Required include directories +BOARDINC = $(BOARD_PATH)/board + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC  += $(BOARDINC) diff --git a/platforms/chibios/GENERIC_STM32_F042X6/configs/bootloader_defs.h b/platforms/chibios/GENERIC_STM32_F042X6/configs/bootloader_defs.h new file mode 100644 index 0000000000..4994be9c24 --- /dev/null +++ b/platforms/chibios/GENERIC_STM32_F042X6/configs/bootloader_defs.h @@ -0,0 +1,7 @@ +/* Address for jumping to bootloader on STM32 chips. */ +/* It is chip dependent, the correct number can be looked up here: + * http://www.st.com/web/en/resource/technical/document/application_note/CD00167594.pdf + * This also requires a patch to chibios: + *  <tmk_dir>/tmk_core/tool/chibios/ch-bootloader-jump.patch + */ +#define STM32_BOOTLOADER_ADDRESS 0x1FFFC400
\ No newline at end of file diff --git a/platforms/chibios/GENERIC_STM32_F072XB/board/board.c b/platforms/chibios/GENERIC_STM32_F072XB/board/board.c new file mode 100644 index 0000000000..c91136e8f6 --- /dev/null +++ b/platforms/chibios/GENERIC_STM32_F072XB/board/board.c @@ -0,0 +1,250 @@ +/* +    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + +    Licensed under the Apache License, Version 2.0 (the "License"); +    you may not use this file except in compliance with the License. +    You may obtain a copy of the License at + +        http://www.apache.org/licenses/LICENSE-2.0 + +    Unless required by applicable law or agreed to in writing, software +    distributed under the License is distributed on an "AS IS" BASIS, +    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +    See the License for the specific language governing permissions and +    limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#include "hal.h" +#include "stm32_gpio.h" + +/*===========================================================================*/ +/* Driver local definitions.                                                 */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables.                                                */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types.                                         */ +/*===========================================================================*/ + +/** + * @brief   Type of STM32 GPIO port setup. + */ +typedef struct { +    uint32_t moder; +    uint32_t otyper; +    uint32_t ospeedr; +    uint32_t pupdr; +    uint32_t odr; +    uint32_t afrl; +    uint32_t afrh; +} gpio_setup_t; + +/** + * @brief   Type of STM32 GPIO initialization data. + */ +typedef struct { +#if STM32_HAS_GPIOA || defined(__DOXYGEN__) +    gpio_setup_t PAData; +#endif +#if STM32_HAS_GPIOB || defined(__DOXYGEN__) +    gpio_setup_t PBData; +#endif +#if STM32_HAS_GPIOC || defined(__DOXYGEN__) +    gpio_setup_t PCData; +#endif +#if STM32_HAS_GPIOD || defined(__DOXYGEN__) +    gpio_setup_t PDData; +#endif +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) +    gpio_setup_t PEData; +#endif +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) +    gpio_setup_t PFData; +#endif +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) +    gpio_setup_t PGData; +#endif +#if STM32_HAS_GPIOH || defined(__DOXYGEN__) +    gpio_setup_t PHData; +#endif +#if STM32_HAS_GPIOI || defined(__DOXYGEN__) +    gpio_setup_t PIData; +#endif +#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) +    gpio_setup_t PJData; +#endif +#if STM32_HAS_GPIOK || defined(__DOXYGEN__) +    gpio_setup_t PKData; +#endif +} gpio_config_t; + +/** + * @brief   STM32 GPIO static initialization data. + */ +static const gpio_config_t gpio_default_config = { +#if STM32_HAS_GPIOA +    {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB +    {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC +    {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD +    {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE +    {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +#if STM32_HAS_GPIOF +    {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +#endif +#if STM32_HAS_GPIOG +    {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +#endif +#if STM32_HAS_GPIOH +    {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +#if STM32_HAS_GPIOI +    {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, +#endif +#if STM32_HAS_GPIOJ +    {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, +#endif +#if STM32_HAS_GPIOK +    {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} +#endif +}; + +/*===========================================================================*/ +/* Driver local functions.                                                   */ +/*===========================================================================*/ + +static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { +    gpiop->OTYPER  = config->otyper; +    gpiop->OSPEEDR = config->ospeedr; +    gpiop->PUPDR   = config->pupdr; +    gpiop->ODR     = config->odr; +    gpiop->AFRL    = config->afrl; +    gpiop->AFRH    = config->afrh; +    gpiop->MODER   = config->moder; +} + +static void stm32_gpio_init(void) { +    /* Enabling GPIO-related clocks, the mask comes from the +       registry header file.*/ +    rccResetAHB(STM32_GPIO_EN_MASK); +    rccEnableAHB(STM32_GPIO_EN_MASK, true); + +    /* Initializing all the defined GPIO ports.*/ +#if STM32_HAS_GPIOA +    gpio_init(GPIOA, &gpio_default_config.PAData); +#endif +#if STM32_HAS_GPIOB +    gpio_init(GPIOB, &gpio_default_config.PBData); +#endif +#if STM32_HAS_GPIOC +    gpio_init(GPIOC, &gpio_default_config.PCData); +#endif +#if STM32_HAS_GPIOD +    gpio_init(GPIOD, &gpio_default_config.PDData); +#endif +#if STM32_HAS_GPIOE +    gpio_init(GPIOE, &gpio_default_config.PEData); +#endif +#if STM32_HAS_GPIOF +    gpio_init(GPIOF, &gpio_default_config.PFData); +#endif +#if STM32_HAS_GPIOG +    gpio_init(GPIOG, &gpio_default_config.PGData); +#endif +#if STM32_HAS_GPIOH +    gpio_init(GPIOH, &gpio_default_config.PHData); +#endif +#if STM32_HAS_GPIOI +    gpio_init(GPIOI, &gpio_default_config.PIData); +#endif +#if STM32_HAS_GPIOJ +    gpio_init(GPIOJ, &gpio_default_config.PJData); +#endif +#if STM32_HAS_GPIOK +    gpio_init(GPIOK, &gpio_default_config.PKData); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers.                                                */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions.                                                */ +/*===========================================================================*/ + +__attribute__((weak)) void enter_bootloader_mode_if_requested(void) {} + +/** + * @brief   Early initialization code. + * @details GPIO ports and system clocks are initialized before everything + *          else. + */ +void __early_init(void) { +    enter_bootloader_mode_if_requested(); + +    stm32_gpio_init(); +    stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief   SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { +    (void)sdcp; +    /* TODO: Fill the implementation.*/ +    return true; +} + +/** + * @brief   SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { +    (void)sdcp; +    /* TODO: Fill the implementation.*/ +    return false; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief   MMC_SPI card detection. + */ +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { +    (void)mmcp; +    /* TODO: Fill the implementation.*/ +    return true; +} + +/** + * @brief   MMC_SPI card write protection detection. + */ +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { +    (void)mmcp; +    /* TODO: Fill the implementation.*/ +    return false; +} +#endif + +/** + * @brief   Board-specific initialization code. + * @todo    Add your board-specific code, if any. + */ +void boardInit(void) {} diff --git a/platforms/chibios/GENERIC_STM32_F072XB/board/board.h b/platforms/chibios/GENERIC_STM32_F072XB/board/board.h new file mode 100644 index 0000000000..87570e62d2 --- /dev/null +++ b/platforms/chibios/GENERIC_STM32_F072XB/board/board.h @@ -0,0 +1,407 @@ +/* +    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + +    Licensed under the Apache License, Version 2.0 (the "License"); +    you may not use this file except in compliance with the License. +    You may obtain a copy of the License at + +        http://www.apache.org/licenses/LICENSE-2.0 + +    Unless required by applicable law or agreed to in writing, software +    distributed under the License is distributed on an "AS IS" BASIS, +    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +    See the License for the specific language governing permissions and +    limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#ifndef BOARD_H +#define BOARD_H + +/*===========================================================================*/ +/* Driver constants.                                                         */ +/*===========================================================================*/ + +/* + * Setup for Generic STM32_F072 Board + */ + +/* + * Board identifier. + */ +#define BOARD_GENERIC_STM32_F072XB +#define BOARD_NAME "STM32_F072" + +/* + * Board oscillators-related settings. + * NOTE: LSE not fitted. + * NOTE: HSE not fitted. + */ +#if !defined(STM32_LSECLK) +#    define STM32_LSECLK 0U +#endif + +#define STM32_LSEDRV (3U << 3U) + +#if !defined(STM32_HSECLK) +#    define STM32_HSECLK 0U +#endif + +#define STM32_HSE_BYPASS + +/* + * MCU type as defined in the ST header. + */ +#define STM32F072xB + +/* + * IO pins assignments. + */ +#define GPIOA_BUTTON 0U +#define GPIOA_PIN1 1U +#define GPIOA_PIN2 2U +#define GPIOA_PIN3 3U +#define GPIOA_PIN4 4U +#define GPIOA_PIN5 5U +#define GPIOA_PIN6 6U +#define GPIOA_PIN7 7U +#define GPIOA_PIN8 8U +#define GPIOA_PIN9 9U +#define GPIOA_PIN10 10U +#define GPIOA_USB_DM 11U +#define GPIOA_USB_DP 12U +#define GPIOA_SWDIO 13U +#define GPIOA_SWCLK 14U +#define GPIOA_PIN15 15U + +#define GPIOB_PIN0 0U +#define GPIOB_PIN1 1U +#define GPIOB_PIN2 2U +#define GPIOB_PIN3 3U +#define GPIOB_PIN4 4U +#define GPIOB_PIN5 5U +#define GPIOB_PIN6 6U +#define GPIOB_PIN7 7U +#define GPIOB_PIN8 8U +#define GPIOB_PIN9 9U +#define GPIOB_PIN10 10U +#define GPIOB_PIN11 11U +#define GPIOB_PIN12 12U +#define GPIOB_SPI2_SCK 13U +#define GPIOB_SPI2_MISO 14U +#define GPIOB_SPI2_MOSI 15U + +#define GPIOC_MEMS_CS 0U +#define GPIOC_PIN1 1U +#define GPIOC_PIN2 2U +#define GPIOC_PIN3 3U +#define GPIOC_PIN4 4U +#define GPIOC_PIN5 5U +#define GPIOC_LED_RED 6U +#define GPIOC_LED_BLUE 7U +#define GPIOC_LED_ORANGE 8U +#define GPIOC_LED_GREEN 9U +#define GPIOC_PIN10 10U +#define GPIOC_PIN11 11U +#define GPIOC_PIN12 12U +#define GPIOC_PIN13 13U +#define GPIOC_OSC32_IN 14U +#define GPIOC_OSC32_OUT 15U + +#define GPIOD_PIN0 0U +#define GPIOD_PIN1 1U +#define GPIOD_PIN2 2U +#define GPIOD_PIN3 3U +#define GPIOD_PIN4 4U +#define GPIOD_PIN5 5U +#define GPIOD_PIN6 6U +#define GPIOD_PIN7 7U +#define GPIOD_PIN8 8U +#define GPIOD_PIN9 9U +#define GPIOD_PIN10 10U +#define GPIOD_PIN11 11U +#define GPIOD_PIN12 12U +#define GPIOD_PIN13 13U +#define GPIOD_PIN14 14U +#define GPIOD_PIN15 15U + +#define GPIOE_PIN0 0U +#define GPIOE_PIN1 1U +#define GPIOE_PIN2 2U +#define GPIOE_PIN3 3U +#define GPIOE_PIN4 4U +#define GPIOE_PIN5 5U +#define GPIOE_PIN6 6U +#define GPIOE_PIN7 7U +#define GPIOE_PIN8 8U +#define GPIOE_PIN9 9U +#define GPIOE_PIN10 10U +#define GPIOE_PIN11 11U +#define GPIOE_PIN12 12U +#define GPIOE_PIN13 13U +#define GPIOE_PIN14 14U +#define GPIOE_PIN15 15U + +#define GPIOF_OSC_IN 0U +#define GPIOF_OSC_OUT 1U +#define GPIOF_PIN2 2U +#define GPIOF_PIN3 3U +#define GPIOF_PIN4 4U +#define GPIOF_PIN5 5U +#define GPIOF_PIN6 6U +#define GPIOF_PIN7 7U +#define GPIOF_PIN8 8U +#define GPIOF_PIN9 9U +#define GPIOF_PIN10 10U +#define GPIOF_PIN11 11U +#define GPIOF_PIN12 12U +#define GPIOF_PIN13 13U +#define GPIOF_PIN14 14U +#define GPIOF_PIN15 15U + +/* + * IO lines assignments. + */ +#define LINE_BUTTON PAL_LINE(GPIOA, 0U) +#define LINE_USB_DM PAL_LINE(GPIOA, 11U) +#define LINE_USB_DP PAL_LINE(GPIOA, 12U) +#define LINE_SWDIO PAL_LINE(GPIOA, 13U) +#define LINE_SWCLK PAL_LINE(GPIOA, 14U) +#define LINE_SPI2_SCK PAL_LINE(GPIOB, 13U) +#define LINE_SPI2_MISO PAL_LINE(GPIOB, 14U) +#define LINE_SPI2_MOSI PAL_LINE(GPIOB, 15U) +#define LINE_MEMS_CS PAL_LINE(GPIOC, 0U) +#define LINE_LED_RED PAL_LINE(GPIOC, 6U) +#define LINE_LED_BLUE PAL_LINE(GPIOC, 7U) +#define LINE_LED_ORANGE PAL_LINE(GPIOC, 8U) +#define LINE_LED_GREEN PAL_LINE(GPIOC, 9U) +#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U) +#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U) +#define LINE_OSC_IN PAL_LINE(GPIOF, 0U) +#define LINE_OSC_OUT PAL_LINE(GPIOF, 1U) + +/*===========================================================================*/ +/* Driver pre-compile time settings.                                         */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks.                                       */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types.                                         */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros.                                                            */ +/*===========================================================================*/ + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n)*2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n)*2U)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n)*2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n)*2U)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_VERYLOW(n) (0U << ((n)*2U)) +#define PIN_OSPEED_LOW(n) (1U << ((n)*2U)) +#define PIN_OSPEED_MEDIUM(n) (2U << ((n)*2U)) +#define PIN_OSPEED_HIGH(n) (3U << ((n)*2U)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n)*2U)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n)*2U)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n)*2U)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) + +/* + * GPIOA setup: + * + * PA0  - BUTTON                    (input floating). + * PA1  - PIN1                      (input pullup). + * PA2  - PIN2                      (input pullup). + * PA3  - PIN3                      (input pullup). + * PA4  - PIN4                      (input pullup). + * PA5  - PIN5                      (input pullup). + * PA6  - PIN6                      (input pullup). + * PA7  - PIN7                      (input pullup). + * PA8  - PIN8                      (input pullup). + * PA9  - PIN9                      (input pullup). + * PA10 - PIN10                     (input pullup). + * PA11 - USB_DM                    (input floating). + * PA12 - USB_DP                    (input floating). + * PA13 - SWDIO                     (alternate 0). + * PA14 - SWCLK                     (alternate 0). + * PA15 - PIN15                     (input pullup). + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON) | PIN_MODE_INPUT(GPIOA_PIN1) | PIN_MODE_INPUT(GPIOA_PIN2) | PIN_MODE_INPUT(GPIOA_PIN3) | PIN_MODE_INPUT(GPIOA_PIN4) | PIN_MODE_INPUT(GPIOA_PIN5) | PIN_MODE_INPUT(GPIOA_PIN6) | PIN_MODE_INPUT(GPIOA_PIN7) | PIN_MODE_INPUT(GPIOA_PIN8) | PIN_MODE_INPUT(GPIOA_PIN9) | PIN_MODE_INPUT(GPIOA_PIN10) | PIN_MODE_INPUT(GPIOA_USB_DM) | PIN_MODE_INPUT(GPIOA_USB_DP) | PIN_MODE_ALTERNATE(GPIOA_SWDIO) | PIN_MODE_ALTERNATE(GPIOA_SWCLK) | PIN_MODE_INPUT(GPIOA_PIN15)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) | PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | PIN_OTYPE_PUSHPULL(GPIOA_PIN9) | PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | PIN_OTYPE_PUSHPULL(GPIOA_USB_DM) | PIN_OTYPE_PUSHPULL(GPIOA_USB_DP) | PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOA_BUTTON) | PIN_OSPEED_VERYLOW(GPIOA_PIN1) | PIN_OSPEED_VERYLOW(GPIOA_PIN2) | PIN_OSPEED_VERYLOW(GPIOA_PIN3) | PIN_OSPEED_VERYLOW(GPIOA_PIN4) | PIN_OSPEED_VERYLOW(GPIOA_PIN5) | PIN_OSPEED_VERYLOW(GPIOA_PIN6) | PIN_OSPEED_VERYLOW(GPIOA_PIN7) | PIN_OSPEED_VERYLOW(GPIOA_PIN8) | PIN_OSPEED_VERYLOW(GPIOA_PIN9) | PIN_OSPEED_VERYLOW(GPIOA_PIN10) | PIN_OSPEED_VERYLOW(GPIOA_USB_DM) | PIN_OSPEED_VERYLOW(GPIOA_USB_DP) | PIN_OSPEED_HIGH(GPIOA_SWDIO) | PIN_OSPEED_HIGH(GPIOA_SWCLK) | PIN_OSPEED_HIGH(GPIOA_PIN15)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON) | PIN_PUPDR_PULLUP(GPIOA_PIN1) | PIN_PUPDR_PULLUP(GPIOA_PIN2) | PIN_PUPDR_PULLUP(GPIOA_PIN3) | PIN_PUPDR_PULLUP(GPIOA_PIN4) | PIN_PUPDR_PULLUP(GPIOA_PIN5) | PIN_PUPDR_PULLUP(GPIOA_PIN6) | PIN_PUPDR_PULLUP(GPIOA_PIN7) | PIN_PUPDR_PULLUP(GPIOA_PIN8) | PIN_PUPDR_PULLUP(GPIOA_PIN9) | PIN_PUPDR_PULLUP(GPIOA_PIN10) | PIN_PUPDR_FLOATING(GPIOA_USB_DM) | PIN_PUPDR_FLOATING(GPIOA_USB_DP) | PIN_PUPDR_PULLUP(GPIOA_SWDIO) | PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | PIN_PUPDR_PULLUP(GPIOA_PIN15)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON) | PIN_ODR_HIGH(GPIOA_PIN1) | PIN_ODR_HIGH(GPIOA_PIN2) | PIN_ODR_HIGH(GPIOA_PIN3) | PIN_ODR_HIGH(GPIOA_PIN4) | PIN_ODR_HIGH(GPIOA_PIN5) | PIN_ODR_HIGH(GPIOA_PIN6) | PIN_ODR_HIGH(GPIOA_PIN7) | PIN_ODR_HIGH(GPIOA_PIN8) | PIN_ODR_HIGH(GPIOA_PIN9) | PIN_ODR_HIGH(GPIOA_PIN10) | PIN_ODR_HIGH(GPIOA_USB_DM) | PIN_ODR_HIGH(GPIOA_USB_DP) | PIN_ODR_HIGH(GPIOA_SWDIO) | PIN_ODR_HIGH(GPIOA_SWCLK) | PIN_ODR_HIGH(GPIOA_PIN15)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON, 0U) | PIN_AFIO_AF(GPIOA_PIN1, 0U) | PIN_AFIO_AF(GPIOA_PIN2, 0U) | PIN_AFIO_AF(GPIOA_PIN3, 0U) | PIN_AFIO_AF(GPIOA_PIN4, 0U) | PIN_AFIO_AF(GPIOA_PIN5, 0U) | PIN_AFIO_AF(GPIOA_PIN6, 0U) | PIN_AFIO_AF(GPIOA_PIN7, 0U)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0U) | PIN_AFIO_AF(GPIOA_PIN9, 0U) | PIN_AFIO_AF(GPIOA_PIN10, 0U) | PIN_AFIO_AF(GPIOA_USB_DM, 0U) | PIN_AFIO_AF(GPIOA_USB_DP, 0U) | PIN_AFIO_AF(GPIOA_SWDIO, 0U) | PIN_AFIO_AF(GPIOA_SWCLK, 0U) | PIN_AFIO_AF(GPIOA_PIN15, 0U)) + +/* + * GPIOB setup: + * + * PB0  - PIN0                      (input pullup). + * PB1  - PIN1                      (input pullup). + * PB2  - PIN2                      (input pullup). + * PB3  - PIN3                      (input pullup). + * PB4  - PIN4                      (input pullup). + * PB5  - PIN5                      (input pullup). + * PB6  - PIN6                      (input pullup). + * PB7  - PIN7                      (input pullup). + * PB8  - PIN8                      (input pullup). + * PB9  - PIN9                      (input pullup). + * PB10 - PIN10                     (input pullup). + * PB11 - PIN11                     (input pullup). + * PB12 - PIN12                     (input pullup). + * PB13 - SPI2_SCK                  (alternate 0). + * PB14 - SPI2_MISO                 (alternate 0). + * PB15 - SPI2_MOSI                 (alternate 0). + */ +#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | PIN_MODE_INPUT(GPIOB_PIN1) | PIN_MODE_INPUT(GPIOB_PIN2) | PIN_MODE_INPUT(GPIOB_PIN3) | PIN_MODE_INPUT(GPIOB_PIN4) | PIN_MODE_INPUT(GPIOB_PIN5) | PIN_MODE_INPUT(GPIOB_PIN6) | PIN_MODE_INPUT(GPIOB_PIN7) | PIN_MODE_INPUT(GPIOB_PIN8) | PIN_MODE_INPUT(GPIOB_PIN9) | PIN_MODE_INPUT(GPIOB_PIN10) | PIN_MODE_INPUT(GPIOB_PIN11) | PIN_MODE_INPUT(GPIOB_PIN12) | PIN_MODE_ALTERNATE(GPIOB_SPI2_SCK) | PIN_MODE_ALTERNATE(GPIOB_SPI2_MISO) | PIN_MODE_ALTERNATE(GPIOB_SPI2_MOSI)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | PIN_OTYPE_PUSHPULL(GPIOB_PIN3) | PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | PIN_OTYPE_PUSHPULL(GPIOB_SPI2_SCK) | PIN_OTYPE_PUSHPULL(GPIOB_SPI2_MISO) | PIN_OTYPE_PUSHPULL(GPIOB_SPI2_MOSI)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOB_PIN0) | PIN_OSPEED_VERYLOW(GPIOB_PIN1) | PIN_OSPEED_HIGH(GPIOB_PIN2) | PIN_OSPEED_HIGH(GPIOB_PIN3) | PIN_OSPEED_HIGH(GPIOB_PIN4) | PIN_OSPEED_VERYLOW(GPIOB_PIN5) | PIN_OSPEED_VERYLOW(GPIOB_PIN6) | PIN_OSPEED_VERYLOW(GPIOB_PIN7) | PIN_OSPEED_VERYLOW(GPIOB_PIN8) | PIN_OSPEED_VERYLOW(GPIOB_PIN9) | PIN_OSPEED_VERYLOW(GPIOB_PIN10) | PIN_OSPEED_VERYLOW(GPIOB_PIN11) | PIN_OSPEED_VERYLOW(GPIOB_PIN12) | PIN_OSPEED_VERYLOW(GPIOB_SPI2_SCK) | PIN_OSPEED_VERYLOW(GPIOB_SPI2_MISO) | PIN_OSPEED_VERYLOW(GPIOB_SPI2_MOSI)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | PIN_PUPDR_PULLUP(GPIOB_PIN1) | PIN_PUPDR_PULLUP(GPIOB_PIN2) | PIN_PUPDR_PULLUP(GPIOB_PIN3) | PIN_PUPDR_PULLUP(GPIOB_PIN4) | PIN_PUPDR_PULLUP(GPIOB_PIN5) | PIN_PUPDR_PULLUP(GPIOB_PIN6) | PIN_PUPDR_PULLUP(GPIOB_PIN7) | PIN_PUPDR_PULLUP(GPIOB_PIN8) | PIN_PUPDR_PULLUP(GPIOB_PIN9) | PIN_PUPDR_PULLUP(GPIOB_PIN10) | PIN_PUPDR_PULLUP(GPIOB_PIN11) | PIN_PUPDR_PULLUP(GPIOB_PIN12) | PIN_PUPDR_FLOATING(GPIOB_SPI2_SCK) | PIN_PUPDR_FLOATING(GPIOB_SPI2_MISO) | PIN_PUPDR_FLOATING(GPIOB_SPI2_MOSI)) +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | PIN_ODR_HIGH(GPIOB_PIN1) | PIN_ODR_HIGH(GPIOB_PIN2) | PIN_ODR_HIGH(GPIOB_PIN3) | PIN_ODR_HIGH(GPIOB_PIN4) | PIN_ODR_HIGH(GPIOB_PIN5) | PIN_ODR_HIGH(GPIOB_PIN6) | PIN_ODR_HIGH(GPIOB_PIN7) | PIN_ODR_HIGH(GPIOB_PIN8) | PIN_ODR_HIGH(GPIOB_PIN9) | PIN_ODR_HIGH(GPIOB_PIN10) | PIN_ODR_HIGH(GPIOB_PIN11) | PIN_ODR_HIGH(GPIOB_PIN12) | PIN_ODR_HIGH(GPIOB_SPI2_SCK) | PIN_ODR_HIGH(GPIOB_SPI2_MISO) | PIN_ODR_HIGH(GPIOB_SPI2_MOSI)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | PIN_AFIO_AF(GPIOB_PIN1, 0U) | PIN_AFIO_AF(GPIOB_PIN2, 0U) | PIN_AFIO_AF(GPIOB_PIN3, 0U) | PIN_AFIO_AF(GPIOB_PIN4, 0U) | PIN_AFIO_AF(GPIOB_PIN5, 0U) | PIN_AFIO_AF(GPIOB_PIN6, 0U) | PIN_AFIO_AF(GPIOB_PIN7, 0U)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | PIN_AFIO_AF(GPIOB_PIN9, 0U) | PIN_AFIO_AF(GPIOB_PIN10, 0U) | PIN_AFIO_AF(GPIOB_PIN11, 0U) | PIN_AFIO_AF(GPIOB_PIN12, 0U) | PIN_AFIO_AF(GPIOB_SPI2_SCK, 0U) | PIN_AFIO_AF(GPIOB_SPI2_MISO, 0U) | PIN_AFIO_AF(GPIOB_SPI2_MOSI, 0U)) + +/* + * GPIOC setup: + * + * PC0  - MEMS_CS                   (output pushpull maximum). + * PC1  - PIN1                      (input pullup). + * PC2  - PIN2                      (input pullup). + * PC3  - PIN3                      (input pullup). + * PC4  - PIN4                      (input pullup). + * PC5  - PIN5                      (input pullup). + * PC6  - LED_RED                   (output pushpull maximum). + * PC7  - LED_BLUE                  (output pushpull maximum). + * PC8  - LED_ORANGE                (output pushpull maximum). + * PC9  - LED_GREEN                 (output pushpull maximum). + * PC10 - PIN10                     (input pullup). + * PC11 - PIN11                     (input pullup). + * PC12 - PIN12                     (input pullup). + * PC13 - PIN13                     (input pullup). + * PC14 - OSC32_IN                  (input floating). + * PC15 - OSC32_OUT                 (input floating). + */ +#define VAL_GPIOC_MODER (PIN_MODE_OUTPUT(GPIOC_MEMS_CS) | PIN_MODE_INPUT(GPIOC_PIN1) | PIN_MODE_INPUT(GPIOC_PIN2) | PIN_MODE_INPUT(GPIOC_PIN3) | PIN_MODE_INPUT(GPIOC_PIN4) | PIN_MODE_INPUT(GPIOC_PIN5) | PIN_MODE_OUTPUT(GPIOC_LED_RED) | PIN_MODE_OUTPUT(GPIOC_LED_BLUE) | PIN_MODE_OUTPUT(GPIOC_LED_ORANGE) | PIN_MODE_OUTPUT(GPIOC_LED_GREEN) | PIN_MODE_INPUT(GPIOC_PIN10) | PIN_MODE_INPUT(GPIOC_PIN11) | PIN_MODE_INPUT(GPIOC_PIN12) | PIN_MODE_INPUT(GPIOC_PIN13) | PIN_MODE_INPUT(GPIOC_OSC32_IN) | PIN_MODE_INPUT(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_MEMS_CS) | PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | PIN_OTYPE_PUSHPULL(GPIOC_LED_RED) | PIN_OTYPE_PUSHPULL(GPIOC_LED_BLUE) | PIN_OTYPE_PUSHPULL(GPIOC_LED_ORANGE) | PIN_OTYPE_PUSHPULL(GPIOC_LED_GREEN) | PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_MEMS_CS) | PIN_OSPEED_VERYLOW(GPIOC_PIN1) | PIN_OSPEED_VERYLOW(GPIOC_PIN2) | PIN_OSPEED_VERYLOW(GPIOC_PIN3) | PIN_OSPEED_VERYLOW(GPIOC_PIN4) | PIN_OSPEED_VERYLOW(GPIOC_PIN5) | PIN_OSPEED_HIGH(GPIOC_LED_RED) | PIN_OSPEED_HIGH(GPIOC_LED_BLUE) | PIN_OSPEED_HIGH(GPIOC_LED_ORANGE) | PIN_OSPEED_HIGH(GPIOC_LED_GREEN) | PIN_OSPEED_VERYLOW(GPIOC_PIN10) | PIN_OSPEED_VERYLOW(GPIOC_PIN11) | PIN_OSPEED_VERYLOW(GPIOC_PIN12) | PIN_OSPEED_VERYLOW(GPIOC_PIN13) | PIN_OSPEED_HIGH(GPIOC_OSC32_IN) | PIN_OSPEED_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_MEMS_CS) | PIN_PUPDR_PULLUP(GPIOC_PIN1) | PIN_PUPDR_PULLUP(GPIOC_PIN2) | PIN_PUPDR_PULLUP(GPIOC_PIN3) | PIN_PUPDR_PULLUP(GPIOC_PIN4) | PIN_PUPDR_PULLUP(GPIOC_PIN5) | PIN_PUPDR_FLOATING(GPIOC_LED_RED) | PIN_PUPDR_FLOATING(GPIOC_LED_BLUE) | PIN_PUPDR_FLOATING(GPIOC_LED_ORANGE) | PIN_PUPDR_FLOATING(GPIOC_LED_GREEN) | PIN_PUPDR_PULLUP(GPIOC_PIN10) | PIN_PUPDR_PULLUP(GPIOC_PIN11) | PIN_PUPDR_PULLUP(GPIOC_PIN12) | PIN_PUPDR_PULLUP(GPIOC_PIN13) | PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_MEMS_CS) | PIN_ODR_HIGH(GPIOC_PIN1) | PIN_ODR_HIGH(GPIOC_PIN2) | PIN_ODR_HIGH(GPIOC_PIN3) | PIN_ODR_HIGH(GPIOC_PIN4) | PIN_ODR_HIGH(GPIOC_PIN5) | PIN_ODR_LOW(GPIOC_LED_RED) | PIN_ODR_LOW(GPIOC_LED_BLUE) | PIN_ODR_LOW(GPIOC_LED_ORANGE) | PIN_ODR_LOW(GPIOC_LED_GREEN) | PIN_ODR_HIGH(GPIOC_PIN10) | PIN_ODR_HIGH(GPIOC_PIN11) | PIN_ODR_HIGH(GPIOC_PIN12) | PIN_ODR_HIGH(GPIOC_PIN13) | PIN_ODR_HIGH(GPIOC_OSC32_IN) | PIN_ODR_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_MEMS_CS, 0U) | PIN_AFIO_AF(GPIOC_PIN1, 0U) | PIN_AFIO_AF(GPIOC_PIN2, 0U) | PIN_AFIO_AF(GPIOC_PIN3, 0U) | PIN_AFIO_AF(GPIOC_PIN4, 0U) | PIN_AFIO_AF(GPIOC_PIN5, 0U) | PIN_AFIO_AF(GPIOC_LED_RED, 0U) | PIN_AFIO_AF(GPIOC_LED_BLUE, 0U)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_LED_ORANGE, 0U) | PIN_AFIO_AF(GPIOC_LED_GREEN, 0U) | PIN_AFIO_AF(GPIOC_PIN10, 0U) | PIN_AFIO_AF(GPIOC_PIN11, 0U) | PIN_AFIO_AF(GPIOC_PIN12, 0U) | PIN_AFIO_AF(GPIOC_PIN13, 0U) | PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U)) + +/* + * GPIOD setup: + * + * PD0  - PIN0                      (input pullup). + * PD1  - PIN1                      (input pullup). + * PD2  - PIN2                      (input pullup). + * PD3  - PIN3                      (input pullup). + * PD4  - PIN4                      (input pullup). + * PD5  - PIN5                      (input pullup). + * PD6  - PIN6                      (input pullup). + * PD7  - PIN7                      (input pullup). + * PD8  - PIN8                      (input pullup). + * PD9  - PIN9                      (input pullup). + * PD10 - PIN10                     (input pullup). + * PD11 - PIN11                     (input pullup). + * PD12 - PIN12                     (input pullup). + * PD13 - PIN13                     (input pullup). + * PD14 - PIN14                     (input pullup). + * PD15 - PIN15                     (input pullup). + */ +#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | PIN_MODE_INPUT(GPIOD_PIN1) | PIN_MODE_INPUT(GPIOD_PIN2) | PIN_MODE_INPUT(GPIOD_PIN3) | PIN_MODE_INPUT(GPIOD_PIN4) | PIN_MODE_INPUT(GPIOD_PIN5) | PIN_MODE_INPUT(GPIOD_PIN6) | PIN_MODE_INPUT(GPIOD_PIN7) | PIN_MODE_INPUT(GPIOD_PIN8) | PIN_MODE_INPUT(GPIOD_PIN9) | PIN_MODE_INPUT(GPIOD_PIN10) | PIN_MODE_INPUT(GPIOD_PIN11) | PIN_MODE_INPUT(GPIOD_PIN12) | PIN_MODE_INPUT(GPIOD_PIN13) | PIN_MODE_INPUT(GPIOD_PIN14) | PIN_MODE_INPUT(GPIOD_PIN15)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOD_PIN0) | PIN_OSPEED_VERYLOW(GPIOD_PIN1) | PIN_OSPEED_VERYLOW(GPIOD_PIN2) | PIN_OSPEED_VERYLOW(GPIOD_PIN3) | PIN_OSPEED_VERYLOW(GPIOD_PIN4) | PIN_OSPEED_VERYLOW(GPIOD_PIN5) | PIN_OSPEED_VERYLOW(GPIOD_PIN6) | PIN_OSPEED_VERYLOW(GPIOD_PIN7) | PIN_OSPEED_VERYLOW(GPIOD_PIN8) | PIN_OSPEED_VERYLOW(GPIOD_PIN9) | PIN_OSPEED_VERYLOW(GPIOD_PIN10) | PIN_OSPEED_VERYLOW(GPIOD_PIN11) | PIN_OSPEED_VERYLOW(GPIOD_PIN12) | PIN_OSPEED_VERYLOW(GPIOD_PIN13) | PIN_OSPEED_VERYLOW(GPIOD_PIN14) | PIN_OSPEED_VERYLOW(GPIOD_PIN15)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | PIN_PUPDR_PULLUP(GPIOD_PIN1) | PIN_PUPDR_PULLUP(GPIOD_PIN2) | PIN_PUPDR_PULLUP(GPIOD_PIN3) | PIN_PUPDR_PULLUP(GPIOD_PIN4) | PIN_PUPDR_PULLUP(GPIOD_PIN5) | PIN_PUPDR_PULLUP(GPIOD_PIN6) | PIN_PUPDR_PULLUP(GPIOD_PIN7) | PIN_PUPDR_PULLUP(GPIOD_PIN8) | PIN_PUPDR_PULLUP(GPIOD_PIN9) | PIN_PUPDR_PULLUP(GPIOD_PIN10) | PIN_PUPDR_PULLUP(GPIOD_PIN11) | PIN_PUPDR_PULLUP(GPIOD_PIN12) | PIN_PUPDR_PULLUP(GPIOD_PIN13) | PIN_PUPDR_PULLUP(GPIOD_PIN14) | PIN_PUPDR_PULLUP(GPIOD_PIN15)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | PIN_ODR_HIGH(GPIOD_PIN1) | PIN_ODR_HIGH(GPIOD_PIN2) | PIN_ODR_HIGH(GPIOD_PIN3) | PIN_ODR_HIGH(GPIOD_PIN4) | PIN_ODR_HIGH(GPIOD_PIN5) | PIN_ODR_HIGH(GPIOD_PIN6) | PIN_ODR_HIGH(GPIOD_PIN7) | PIN_ODR_HIGH(GPIOD_PIN8) | PIN_ODR_HIGH(GPIOD_PIN9) | PIN_ODR_HIGH(GPIOD_PIN10) | PIN_ODR_HIGH(GPIOD_PIN11) | PIN_ODR_HIGH(GPIOD_PIN12) | PIN_ODR_HIGH(GPIOD_PIN13) | PIN_ODR_HIGH(GPIOD_PIN14) | PIN_ODR_HIGH(GPIOD_PIN15)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | PIN_AFIO_AF(GPIOD_PIN1, 0U) | PIN_AFIO_AF(GPIOD_PIN2, 0U) | PIN_AFIO_AF(GPIOD_PIN3, 0U) | PIN_AFIO_AF(GPIOD_PIN4, 0U) | PIN_AFIO_AF(GPIOD_PIN5, 0U) | PIN_AFIO_AF(GPIOD_PIN6, 0U) | PIN_AFIO_AF(GPIOD_PIN7, 0U)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | PIN_AFIO_AF(GPIOD_PIN9, 0U) | PIN_AFIO_AF(GPIOD_PIN10, 0U) | PIN_AFIO_AF(GPIOD_PIN11, 0U) | PIN_AFIO_AF(GPIOD_PIN12, 0U) | PIN_AFIO_AF(GPIOD_PIN13, 0U) | PIN_AFIO_AF(GPIOD_PIN14, 0U) | PIN_AFIO_AF(GPIOD_PIN15, 0U)) + +/* + * GPIOE setup: + * + * PE0  - PIN0                      (input pullup). + * PE1  - PIN1                      (input pullup). + * PE2  - PIN2                      (input pullup). + * PE3  - PIN3                      (input pullup). + * PE4  - PIN4                      (input pullup). + * PE5  - PIN5                      (input pullup). + * PE6  - PIN6                      (input pullup). + * PE7  - PIN7                      (input pullup). + * PE8  - PIN8                      (input pullup). + * PE9  - PIN9                      (input pullup). + * PE10 - PIN10                     (input pullup). + * PE11 - PIN11                     (input pullup). + * PE12 - PIN12                     (input pullup). + * PE13 - PIN13                     (input pullup). + * PE14 - PIN14                     (input pullup). + * PE15 - PIN15                     (input pullup). + */ +#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | PIN_MODE_INPUT(GPIOE_PIN1) | PIN_MODE_INPUT(GPIOE_PIN2) | PIN_MODE_INPUT(GPIOE_PIN3) | PIN_MODE_INPUT(GPIOE_PIN4) | PIN_MODE_INPUT(GPIOE_PIN5) | PIN_MODE_INPUT(GPIOE_PIN6) | PIN_MODE_INPUT(GPIOE_PIN7) | PIN_MODE_INPUT(GPIOE_PIN8) | PIN_MODE_INPUT(GPIOE_PIN9) | PIN_MODE_INPUT(GPIOE_PIN10) | PIN_MODE_INPUT(GPIOE_PIN11) | PIN_MODE_INPUT(GPIOE_PIN12) | PIN_MODE_INPUT(GPIOE_PIN13) | PIN_MODE_INPUT(GPIOE_PIN14) | PIN_MODE_INPUT(GPIOE_PIN15)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOE_PIN0) | PIN_OSPEED_VERYLOW(GPIOE_PIN1) | PIN_OSPEED_VERYLOW(GPIOE_PIN2) | PIN_OSPEED_VERYLOW(GPIOE_PIN3) | PIN_OSPEED_VERYLOW(GPIOE_PIN4) | PIN_OSPEED_VERYLOW(GPIOE_PIN5) | PIN_OSPEED_VERYLOW(GPIOE_PIN6) | PIN_OSPEED_VERYLOW(GPIOE_PIN7) | PIN_OSPEED_VERYLOW(GPIOE_PIN8) | PIN_OSPEED_VERYLOW(GPIOE_PIN9) | PIN_OSPEED_VERYLOW(GPIOE_PIN10) | PIN_OSPEED_VERYLOW(GPIOE_PIN11) | PIN_OSPEED_VERYLOW(GPIOE_PIN12) | PIN_OSPEED_VERYLOW(GPIOE_PIN13) | PIN_OSPEED_VERYLOW(GPIOE_PIN14) | PIN_OSPEED_VERYLOW(GPIOE_PIN15)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | PIN_PUPDR_PULLUP(GPIOE_PIN1) | PIN_PUPDR_PULLUP(GPIOE_PIN2) | PIN_PUPDR_PULLUP(GPIOE_PIN3) | PIN_PUPDR_PULLUP(GPIOE_PIN4) | PIN_PUPDR_PULLUP(GPIOE_PIN5) | PIN_PUPDR_PULLUP(GPIOE_PIN6) | PIN_PUPDR_PULLUP(GPIOE_PIN7) | PIN_PUPDR_PULLUP(GPIOE_PIN8) | PIN_PUPDR_PULLUP(GPIOE_PIN9) | PIN_PUPDR_PULLUP(GPIOE_PIN10) | PIN_PUPDR_PULLUP(GPIOE_PIN11) | PIN_PUPDR_PULLUP(GPIOE_PIN12) | PIN_PUPDR_PULLUP(GPIOE_PIN13) | PIN_PUPDR_PULLUP(GPIOE_PIN14) | PIN_PUPDR_PULLUP(GPIOE_PIN15)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | PIN_ODR_HIGH(GPIOE_PIN1) | PIN_ODR_HIGH(GPIOE_PIN2) | PIN_ODR_HIGH(GPIOE_PIN3) | PIN_ODR_HIGH(GPIOE_PIN4) | PIN_ODR_HIGH(GPIOE_PIN5) | PIN_ODR_HIGH(GPIOE_PIN6) | PIN_ODR_HIGH(GPIOE_PIN7) | PIN_ODR_HIGH(GPIOE_PIN8) | PIN_ODR_HIGH(GPIOE_PIN9) | PIN_ODR_HIGH(GPIOE_PIN10) | PIN_ODR_HIGH(GPIOE_PIN11) | PIN_ODR_HIGH(GPIOE_PIN12) | PIN_ODR_HIGH(GPIOE_PIN13) | PIN_ODR_HIGH(GPIOE_PIN14) | PIN_ODR_HIGH(GPIOE_PIN15)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | PIN_AFIO_AF(GPIOE_PIN1, 0U) | PIN_AFIO_AF(GPIOE_PIN2, 0U) | PIN_AFIO_AF(GPIOE_PIN3, 0U) | PIN_AFIO_AF(GPIOE_PIN4, 0U) | PIN_AFIO_AF(GPIOE_PIN5, 0U) | PIN_AFIO_AF(GPIOE_PIN6, 0U) | PIN_AFIO_AF(GPIOE_PIN7, 0U)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | PIN_AFIO_AF(GPIOE_PIN9, 0U) | PIN_AFIO_AF(GPIOE_PIN10, 0U) | PIN_AFIO_AF(GPIOE_PIN11, 0U) | PIN_AFIO_AF(GPIOE_PIN12, 0U) | PIN_AFIO_AF(GPIOE_PIN13, 0U) | PIN_AFIO_AF(GPIOE_PIN14, 0U) | PIN_AFIO_AF(GPIOE_PIN15, 0U)) + +/* + * GPIOF setup: + * + * PF0  - OSC_IN                    (input floating). + * PF1  - OSC_OUT                   (input floating). + * PF2  - PIN2                      (input pullup). + * PF3  - PIN3                      (input pullup). + * PF4  - PIN4                      (input pullup). + * PF5  - PIN5                      (input pullup). + * PF6  - PIN6                      (input pullup). + * PF7  - PIN7                      (input pullup). + * PF8  - PIN8                      (input pullup). + * PF9  - PIN9                      (input pullup). + * PF10 - PIN10                     (input pullup). + * PF11 - PIN11                     (input pullup). + * PF12 - PIN12                     (input pullup). + * PF13 - PIN13                     (input pullup). + * PF14 - PIN14                     (input pullup). + * PF15 - PIN15                     (input pullup). + */ +#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_OSC_IN) | PIN_MODE_INPUT(GPIOF_OSC_OUT) | PIN_MODE_INPUT(GPIOF_PIN2) | PIN_MODE_INPUT(GPIOF_PIN3) | PIN_MODE_INPUT(GPIOF_PIN4) | PIN_MODE_INPUT(GPIOF_PIN5) | PIN_MODE_INPUT(GPIOF_PIN6) | PIN_MODE_INPUT(GPIOF_PIN7) | PIN_MODE_INPUT(GPIOF_PIN8) | PIN_MODE_INPUT(GPIOF_PIN9) | PIN_MODE_INPUT(GPIOF_PIN10) | PIN_MODE_INPUT(GPIOF_PIN11) | PIN_MODE_INPUT(GPIOF_PIN12) | PIN_MODE_INPUT(GPIOF_PIN13) | PIN_MODE_INPUT(GPIOF_PIN14) | PIN_MODE_INPUT(GPIOF_PIN15)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_OSC_IN) | PIN_OTYPE_PUSHPULL(GPIOF_OSC_OUT) | PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOF_OSC_IN) | PIN_OSPEED_VERYLOW(GPIOF_OSC_OUT) | PIN_OSPEED_VERYLOW(GPIOF_PIN2) | PIN_OSPEED_VERYLOW(GPIOF_PIN3) | PIN_OSPEED_VERYLOW(GPIOF_PIN4) | PIN_OSPEED_VERYLOW(GPIOF_PIN5) | PIN_OSPEED_VERYLOW(GPIOF_PIN6) | PIN_OSPEED_VERYLOW(GPIOF_PIN7) | PIN_OSPEED_VERYLOW(GPIOF_PIN8) | PIN_OSPEED_VERYLOW(GPIOF_PIN9) | PIN_OSPEED_VERYLOW(GPIOF_PIN10) | PIN_OSPEED_VERYLOW(GPIOF_PIN11) | PIN_OSPEED_VERYLOW(GPIOF_PIN12) | PIN_OSPEED_VERYLOW(GPIOF_PIN13) | PIN_OSPEED_VERYLOW(GPIOF_PIN14) | PIN_OSPEED_VERYLOW(GPIOF_PIN15)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_OSC_IN) | PIN_PUPDR_FLOATING(GPIOF_OSC_OUT) | PIN_PUPDR_PULLUP(GPIOF_PIN2) | PIN_PUPDR_PULLUP(GPIOF_PIN3) | PIN_PUPDR_PULLUP(GPIOF_PIN4) | PIN_PUPDR_PULLUP(GPIOF_PIN5) | PIN_PUPDR_PULLUP(GPIOF_PIN6) | PIN_PUPDR_PULLUP(GPIOF_PIN7) | PIN_PUPDR_PULLUP(GPIOF_PIN8) | PIN_PUPDR_PULLUP(GPIOF_PIN9) | PIN_PUPDR_PULLUP(GPIOF_PIN10) | PIN_PUPDR_PULLUP(GPIOF_PIN11) | PIN_PUPDR_PULLUP(GPIOF_PIN12) | PIN_PUPDR_PULLUP(GPIOF_PIN13) | PIN_PUPDR_PULLUP(GPIOF_PIN14) | PIN_PUPDR_PULLUP(GPIOF_PIN15)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_OSC_IN) | PIN_ODR_HIGH(GPIOF_OSC_OUT) | PIN_ODR_HIGH(GPIOF_PIN2) | PIN_ODR_HIGH(GPIOF_PIN3) | PIN_ODR_HIGH(GPIOF_PIN4) | PIN_ODR_HIGH(GPIOF_PIN5) | PIN_ODR_HIGH(GPIOF_PIN6) | PIN_ODR_HIGH(GPIOF_PIN7) | PIN_ODR_HIGH(GPIOF_PIN8) | PIN_ODR_HIGH(GPIOF_PIN9) | PIN_ODR_HIGH(GPIOF_PIN10) | PIN_ODR_HIGH(GPIOF_PIN11) | PIN_ODR_HIGH(GPIOF_PIN12) | PIN_ODR_HIGH(GPIOF_PIN13) | PIN_ODR_HIGH(GPIOF_PIN14) | PIN_ODR_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_OSC_IN, 0U) | PIN_AFIO_AF(GPIOF_OSC_OUT, 0U) | PIN_AFIO_AF(GPIOF_PIN2, 0U) | PIN_AFIO_AF(GPIOF_PIN3, 0U) | PIN_AFIO_AF(GPIOF_PIN4, 0U) | PIN_AFIO_AF(GPIOF_PIN5, 0U) | PIN_AFIO_AF(GPIOF_PIN6, 0U) | PIN_AFIO_AF(GPIOF_PIN7, 0U)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | PIN_AFIO_AF(GPIOF_PIN9, 0U) | PIN_AFIO_AF(GPIOF_PIN10, 0U) | PIN_AFIO_AF(GPIOF_PIN11, 0U) | PIN_AFIO_AF(GPIOF_PIN12, 0U) | PIN_AFIO_AF(GPIOF_PIN13, 0U) | PIN_AFIO_AF(GPIOF_PIN14, 0U) | PIN_AFIO_AF(GPIOF_PIN15, 0U)) + +/*===========================================================================*/ +/* External declarations.                                                    */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) +#    ifdef __cplusplus +extern "C" { +#    endif +void boardInit(void); +#    ifdef __cplusplus +} +#    endif +#endif /* _FROM_ASM_ */ + +#endif /* BOARD_H */ diff --git a/platforms/chibios/GENERIC_STM32_F072XB/board/board.mk b/platforms/chibios/GENERIC_STM32_F072XB/board/board.mk new file mode 100644 index 0000000000..842e335905 --- /dev/null +++ b/platforms/chibios/GENERIC_STM32_F072XB/board/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = $(BOARD_PATH)/board/board.c + +# Required include directories +BOARDINC = $(BOARD_PATH)/board + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC  += $(BOARDINC) diff --git a/platforms/chibios/GENERIC_STM32_F072XB/configs/bootloader_defs.h b/platforms/chibios/GENERIC_STM32_F072XB/configs/bootloader_defs.h new file mode 100644 index 0000000000..02c48c4e6d --- /dev/null +++ b/platforms/chibios/GENERIC_STM32_F072XB/configs/bootloader_defs.h @@ -0,0 +1,7 @@ +/* Address for jumping to bootloader on STM32 chips. */ +/* It is chip dependent, the correct number can be looked up here (page 175): + * http://www.st.com/web/en/resource/technical/document/application_note/CD00167594.pdf + * This also requires a patch to chibios: + *  <tmk_dir>/tmk_core/tool/chibios/ch-bootloader-jump.patch + */ +#define STM32_BOOTLOADER_ADDRESS 0x1FFFC800 diff --git a/platforms/chibios/GENERIC_STM32_F303XC/board/board.c b/platforms/chibios/GENERIC_STM32_F303XC/board/board.c new file mode 100644 index 0000000000..4722acd648 --- /dev/null +++ b/platforms/chibios/GENERIC_STM32_F303XC/board/board.c @@ -0,0 +1,242 @@ +/* +    ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + +    Licensed under the Apache License, Version 2.0 (the "License"); +    you may not use this file except in compliance with the License. +    You may obtain a copy of the License at + +        http://www.apache.org/licenses/LICENSE-2.0 + +    Unless required by applicable law or agreed to in writing, software +    distributed under the License is distributed on an "AS IS" BASIS, +    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +    See the License for the specific language governing permissions and +    limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#include "hal.h" +#include "stm32_gpio.h" + +/*===========================================================================*/ +/* Driver local definitions.                                                 */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables.                                                */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types.                                         */ +/*===========================================================================*/ + +/** + * @brief   Type of STM32 GPIO port setup. + */ +typedef struct { +    uint32_t moder; +    uint32_t otyper; +    uint32_t ospeedr; +    uint32_t pupdr; +    uint32_t odr; +    uint32_t afrl; +    uint32_t afrh; +} gpio_setup_t; + +/** + * @brief   Type of STM32 GPIO initialization data. + */ +typedef struct { +#if STM32_HAS_GPIOA || defined(__DOXYGEN__) +    gpio_setup_t PAData; +#endif +#if STM32_HAS_GPIOB || defined(__DOXYGEN__) +    gpio_setup_t PBData; +#endif +#if STM32_HAS_GPIOC || defined(__DOXYGEN__) +    gpio_setup_t PCData; +#endif +#if STM32_HAS_GPIOD || defined(__DOXYGEN__) +    gpio_setup_t PDData; +#endif +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) +    gpio_setup_t PEData; +#endif +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) +    gpio_setup_t PFData; +#endif +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) +    gpio_setup_t PGData; +#endif +#if STM32_HAS_GPIOH || defined(__DOXYGEN__) +    gpio_setup_t PHData; +#endif +#if STM32_HAS_GPIOI || defined(__DOXYGEN__) +    gpio_setup_t PIData; +#endif +#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) +    gpio_setup_t PJData; +#endif +#if STM32_HAS_GPIOK || defined(__DOXYGEN__) +    gpio_setup_t PKData; +#endif +} gpio_config_t; + +/** + * @brief   STM32 GPIO static initialization data. + */ +static const gpio_config_t gpio_default_config = { +#if STM32_HAS_GPIOA +    {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB +    {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC +    {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD +    {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE +    {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +#if STM32_HAS_GPIOF +    {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +#endif +#if STM32_HAS_GPIOG +    {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +#endif +#if STM32_HAS_GPIOH +    {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +#if STM32_HAS_GPIOI +    {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, +#endif +#if STM32_HAS_GPIOJ +    {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, +#endif +#if STM32_HAS_GPIOK +    {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} +#endif +}; + +/*===========================================================================*/ +/* Driver local functions.                                                   */ +/*===========================================================================*/ + +static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { +    gpiop->OTYPER  = config->otyper; +    gpiop->OSPEEDR = config->ospeedr; +    gpiop->PUPDR   = config->pupdr; +    gpiop->ODR     = config->odr; +    gpiop->AFRL    = config->afrl; +    gpiop->AFRH    = config->afrh; +    gpiop->MODER   = config->moder; +} + +static void stm32_gpio_init(void) { +    /* Enabling GPIO-related clocks, the mask comes from the +       registry header file.*/ +    rccResetAHB(STM32_GPIO_EN_MASK); +    rccEnableAHB(STM32_GPIO_EN_MASK, true); + +    /* Initializing all the defined GPIO ports.*/ +#if STM32_HAS_GPIOA +    gpio_init(GPIOA, &gpio_default_config.PAData); +#endif +#if STM32_HAS_GPIOB +    gpio_init(GPIOB, &gpio_default_config.PBData); +#endif +#if STM32_HAS_GPIOC +    gpio_init(GPIOC, &gpio_default_config.PCData); +#endif +#if STM32_HAS_GPIOD +    gpio_init(GPIOD, &gpio_default_config.PDData); +#endif +#if STM32_HAS_GPIOE +    gpio_init(GPIOE, &gpio_default_config.PEData); +#endif +#if STM32_HAS_GPIOF +    gpio_init(GPIOF, &gpio_default_config.PFData); +#endif +#if STM32_HAS_GPIOG +    gpio_init(GPIOG, &gpio_default_config.PGData); +#endif +#if STM32_HAS_GPIOH +    gpio_init(GPIOH, &gpio_default_config.PHData); +#endif +#if STM32_HAS_GPIOI +    gpio_init(GPIOI, &gpio_default_config.PIData); +#endif +#if STM32_HAS_GPIOJ +    gpio_init(GPIOJ, &gpio_default_config.PJData); +#endif +#if STM32_HAS_GPIOK +    gpio_init(GPIOK, &gpio_default_config.PKData); +#endif +} + +__attribute__((weak)) void enter_bootloader_mode_if_requested(void) {} + +/** + * @brief   Early initialization code. + * @details This initialization must be performed just after stack setup + *          and before any other initialization. + */ +void __early_init(void) { +    enter_bootloader_mode_if_requested(); + +    stm32_gpio_init(); +    stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief   SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { +    (void)sdcp; +    /* TODO: Fill the implementation.*/ +    return true; +} + +/** + * @brief   SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { +    (void)sdcp; +    /* TODO: Fill the implementation.*/ +    return false; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief   MMC_SPI card detection. + */ +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { +    (void)mmcp; +    /* TODO: Fill the implementation.*/ +    return true; +} + +/** + * @brief   MMC_SPI card write protection detection. + */ +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { +    (void)mmcp; +    /* TODO: Fill the implementation.*/ +    return false; +} +#endif + +/** + * @brief   Board-specific initialization code. + * @todo    Add your board-specific code, if any. + */ +void boardInit(void) {} diff --git a/platforms/chibios/GENERIC_STM32_F303XC/board/board.h b/platforms/chibios/GENERIC_STM32_F303XC/board/board.h new file mode 100644 index 0000000000..3579c82770 --- /dev/null +++ b/platforms/chibios/GENERIC_STM32_F303XC/board/board.h @@ -0,0 +1,475 @@ +/* +    ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + +    Licensed under the Apache License, Version 2.0 (the "License"); +    you may not use this file except in compliance with the License. +    You may obtain a copy of the License at + +        http://www.apache.org/licenses/LICENSE-2.0 + +    Unless required by applicable law or agreed to in writing, software +    distributed under the License is distributed on an "AS IS" BASIS, +    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +    See the License for the specific language governing permissions and +    limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for Generic STM32_F303 Board + */ + +/* + * Board identifier. + */ +#define BOARD_GENERIC_STM32_F303XC +#define BOARD_NAME "STM32_F303" + +/* + * Board oscillators-related settings. + * NOTE: LSE not fitted. + */ +#if !defined(STM32_LSECLK) +#    define STM32_LSECLK 0U +#endif + +#define STM32_LSEDRV (3U << 3U) + +#if !defined(STM32_HSECLK) +#    define STM32_HSECLK 8000000U +#endif + +// #define STM32_HSE_BYPASS + +/* + * MCU type as defined in the ST header. + */ +#define STM32F303xC + +/* + * IO pins assignments. + */ +#define GPIOA_PIN0 0U +#define GPIOA_PIN1 1U +#define GPIOA_PIN2 2U +#define GPIOA_PIN3 3U +#define GPIOA_PIN4 4U +#define GPIOA_PIN5 5U +#define GPIOA_PIN6 6U +#define GPIOA_PIN7 7U +#define GPIOA_PIN8 8U +#define GPIOA_PIN9 9U +#define GPIOA_PIN10 10U +#define GPIOA_USB_DM 11U +#define GPIOA_USB_DP 12U +#define GPIOA_SWDIO 13U +#define GPIOA_SWCLK 14U +#define GPIOA_PIN15 15U + +#define GPIOB_PIN0 0U +#define GPIOB_PIN1 1U +#define GPIOB_PIN2 2U +#define GPIOB_PIN3 3U +#define GPIOB_PIN4 4U +#define GPIOB_PIN5 5U +#define GPIOB_PIN6 6U +#define GPIOB_PIN7 7U +#define GPIOB_PIN8 8U +#define GPIOB_PIN9 9U +#define GPIOB_PIN10 10U +#define GPIOB_PIN11 11U +#define GPIOB_PIN12 12U +#define GPIOB_PIN13 13U +#define GPIOB_PIN14 14U +#define GPIOB_PIN15 15U + +#define GPIOC_PIN0 0U +#define GPIOC_PIN1 1U +#define GPIOC_PIN2 2U +#define GPIOC_PIN3 3U +#define GPIOC_PIN4 4U +#define GPIOC_PIN5 5U +#define GPIOC_PIN6 6U +#define GPIOC_PIN7 7U +#define GPIOC_PIN8 8U +#define GPIOC_PIN9 9U +#define GPIOC_PIN10 10U +#define GPIOC_PIN11 11U +#define GPIOC_PIN12 12U +#define GPIOC_PIN13 13U +#define GPIOC_PIN14 14U +#define GPIOC_PIN15 15U + +#define GPIOD_PIN0 0U +#define GPIOD_PIN1 1U +#define GPIOD_PIN2 2U +#define GPIOD_PIN3 3U +#define GPIOD_PIN4 4U +#define GPIOD_PIN5 5U +#define GPIOD_PIN6 6U +#define GPIOD_PIN7 7U +#define GPIOD_PIN8 8U +#define GPIOD_PIN9 9U +#define GPIOD_PIN10 10U +#define GPIOD_PIN11 11U +#define GPIOD_PIN12 12U +#define GPIOD_PIN13 13U +#define GPIOD_PIN14 14U +#define GPIOD_PIN15 15U + +#define GPIOE_PIN0 0U +#define GPIOE_PIN1 1U +#define GPIOE_PIN2 2U +#define GPIOE_PIN3 3U +#define GPIOE_PIN4 4U +#define GPIOE_PIN5 5U +#define GPIOE_PIN6 6U +#define GPIOE_PIN7 7U +#define GPIOE_PIN8 8U +#define GPIOE_PIN9 9U +#define GPIOE_PIN10 10U +#define GPIOE_PIN11 11U +#define GPIOE_PIN12 12U +#define GPIOE_PIN13 13U +#define GPIOE_PIN14 14U +#define GPIOE_PIN15 15U + +#define GPIOF_I2C2_SDA 0U +#define GPIOF_I2C2_SCL 1U +#define GPIOF_PIN2 2U +#define GPIOF_PIN3 3U +#define GPIOF_PIN4 4U +#define GPIOF_PIN5 5U +#define GPIOF_PIN6 6U +#define GPIOF_PIN7 7U +#define GPIOF_PIN8 8U +#define GPIOF_PIN9 9U +#define GPIOF_PIN10 10U +#define GPIOF_PIN11 11U +#define GPIOF_PIN12 12U +#define GPIOF_PIN13 13U +#define GPIOF_PIN14 14U +#define GPIOF_PIN15 15U + +#define GPIOG_PIN0 0U +#define GPIOG_PIN1 1U +#define GPIOG_PIN2 2U +#define GPIOG_PIN3 3U +#define GPIOG_PIN4 4U +#define GPIOG_PIN5 5U +#define GPIOG_PIN6 6U +#define GPIOG_PIN7 7U +#define GPIOG_PIN8 8U +#define GPIOG_PIN9 9U +#define GPIOG_PIN10 10U +#define GPIOG_PIN11 11U +#define GPIOG_PIN12 12U +#define GPIOG_PIN13 13U +#define GPIOG_PIN14 14U +#define GPIOG_PIN15 15U + +#define GPIOH_PIN0 0U +#define GPIOH_PIN1 1U +#define GPIOH_PIN2 2U +#define GPIOH_PIN3 3U +#define GPIOH_PIN4 4U +#define GPIOH_PIN5 5U +#define GPIOH_PIN6 6U +#define GPIOH_PIN7 7U +#define GPIOH_PIN8 8U +#define GPIOH_PIN9 9U +#define GPIOH_PIN10 10U +#define GPIOH_PIN11 11U +#define GPIOH_PIN12 12U +#define GPIOH_PIN13 13U +#define GPIOH_PIN14 14U +#define GPIOH_PIN15 15U + +/* + * IO lines assignments. + */ +#define LINE_L3GD20_SDI PAL_LINE(GPIOA, 7U) +#define LINE_USB_DM PAL_LINE(GPIOA, 11U) +#define LINE_USB_DP PAL_LINE(GPIOA, 12U) +#define LINE_SWDIO PAL_LINE(GPIOA, 13U) +#define LINE_SWCLK PAL_LINE(GPIOA, 14U) + +#define LINE_PIN6 PAL_LINE(GPIOF, 0U) +#define LINE_PIN7 PAL_LINE(GPIOF, 1U) + +#define LINE_CAPS_LOCK PAL_LINE(GPIOB, 7U) + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n)*2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n)*2U)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n)*2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n)*2U)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_VERYLOW(n) (0U << ((n)*2U)) +#define PIN_OSPEED_LOW(n) (1U << ((n)*2U)) +#define PIN_OSPEED_MEDIUM(n) (2U << ((n)*2U)) +#define PIN_OSPEED_HIGH(n) (3U << ((n)*2U)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n)*2U)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n)*2U)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n)*2U)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) + +/* + * GPIOA setup: + * + * PA0  - NC + * PA1  - NC + * PA2  - COL1 + * PA3  - COL2 + * PA4  - SPEAKER1 + * PA5  - SPEAKER2 + * PA6  - COL3 + * PA7  - COL8 + * PA8  - COL6 + * PA9  - COL7 + * PA10 - ROW5 + * PA11 - USB_DM                    (alternate 14). + * PA12 - USB_DP                    (alternate 14). + * PA13 - SWDIO                     (alternate 0). + * PA14 - SWCLK                     (alternate 0). + * PA15 - ROW4 + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_PIN0) | PIN_MODE_ALTERNATE(GPIOA_PIN1) | PIN_MODE_INPUT(GPIOA_PIN2) | PIN_MODE_INPUT(GPIOA_PIN3) | PIN_MODE_INPUT(GPIOA_PIN4) | PIN_MODE_INPUT(GPIOA_PIN5) | PIN_MODE_INPUT(GPIOA_PIN6) | PIN_MODE_INPUT(GPIOA_PIN7) | PIN_MODE_INPUT(GPIOA_PIN8) | PIN_MODE_INPUT(GPIOA_PIN9) | PIN_MODE_INPUT(GPIOA_PIN10) | PIN_MODE_ALTERNATE(GPIOA_USB_DM) | PIN_MODE_ALTERNATE(GPIOA_USB_DP) | PIN_MODE_ALTERNATE(GPIOA_SWDIO) | PIN_MODE_ALTERNATE(GPIOA_SWCLK) | PIN_MODE_INPUT(GPIOA_PIN15)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) | PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | PIN_OTYPE_PUSHPULL(GPIOA_PIN9) | PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | PIN_OTYPE_PUSHPULL(GPIOA_USB_DM) | PIN_OTYPE_PUSHPULL(GPIOA_USB_DP) | PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOA_PIN0) | PIN_OSPEED_HIGH(GPIOA_PIN1) | PIN_OSPEED_VERYLOW(GPIOA_PIN2) | PIN_OSPEED_VERYLOW(GPIOA_PIN3) | PIN_OSPEED_VERYLOW(GPIOA_PIN4) | PIN_OSPEED_VERYLOW(GPIOA_PIN5) | PIN_OSPEED_VERYLOW(GPIOA_PIN6) | PIN_OSPEED_VERYLOW(GPIOA_PIN7) | PIN_OSPEED_VERYLOW(GPIOA_PIN8) | PIN_OSPEED_VERYLOW(GPIOA_PIN9) | PIN_OSPEED_VERYLOW(GPIOA_PIN10) | PIN_OSPEED_HIGH(GPIOA_USB_DM) | PIN_OSPEED_VERYLOW(GPIOA_USB_DP) | PIN_OSPEED_HIGH(GPIOA_SWDIO) | PIN_OSPEED_HIGH(GPIOA_SWCLK) | PIN_OSPEED_VERYLOW(GPIOA_PIN15)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_PIN0) | PIN_PUPDR_FLOATING(GPIOA_PIN1) | PIN_PUPDR_PULLUP(GPIOA_PIN2) | PIN_PUPDR_PULLUP(GPIOA_PIN3) | PIN_PUPDR_PULLUP(GPIOA_PIN4) | PIN_PUPDR_PULLUP(GPIOA_PIN5) | PIN_PUPDR_PULLUP(GPIOA_PIN6) | PIN_PUPDR_FLOATING(GPIOA_PIN7) | PIN_PUPDR_PULLUP(GPIOA_PIN8) | PIN_PUPDR_PULLUP(GPIOA_PIN9) | PIN_PUPDR_PULLUP(GPIOA_PIN10) | PIN_PUPDR_FLOATING(GPIOA_USB_DM) | PIN_PUPDR_FLOATING(GPIOA_USB_DP) | PIN_PUPDR_PULLUP(GPIOA_SWDIO) | PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | PIN_PUPDR_PULLUP(GPIOA_PIN15)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_PIN0) | PIN_ODR_HIGH(GPIOA_PIN1) | PIN_ODR_HIGH(GPIOA_PIN2) | PIN_ODR_HIGH(GPIOA_PIN3) | PIN_ODR_HIGH(GPIOA_PIN4) | PIN_ODR_HIGH(GPIOA_PIN5) | PIN_ODR_HIGH(GPIOA_PIN6) | PIN_ODR_HIGH(GPIOA_PIN7) | PIN_ODR_HIGH(GPIOA_PIN8) | PIN_ODR_HIGH(GPIOA_PIN9) | PIN_ODR_HIGH(GPIOA_PIN10) | PIN_ODR_HIGH(GPIOA_USB_DM) | PIN_ODR_HIGH(GPIOA_USB_DP) | PIN_ODR_HIGH(GPIOA_SWDIO) | PIN_ODR_HIGH(GPIOA_SWCLK) | PIN_ODR_HIGH(GPIOA_PIN15)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0) | PIN_AFIO_AF(GPIOA_PIN1, 1) | PIN_AFIO_AF(GPIOA_PIN2, 0) | PIN_AFIO_AF(GPIOA_PIN3, 0) | PIN_AFIO_AF(GPIOA_PIN4, 0) | PIN_AFIO_AF(GPIOA_PIN5, 5) | PIN_AFIO_AF(GPIOA_PIN6, 5) | PIN_AFIO_AF(GPIOA_PIN7, 5)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0) | PIN_AFIO_AF(GPIOA_PIN9, 0) | PIN_AFIO_AF(GPIOA_PIN10, 0) | PIN_AFIO_AF(GPIOA_USB_DM, 14) | PIN_AFIO_AF(GPIOA_USB_DP, 14) | PIN_AFIO_AF(GPIOA_SWDIO, 0) | PIN_AFIO_AF(GPIOA_SWCLK, 0) | PIN_AFIO_AF(GPIOA_PIN15, 0)) + +/* + * GPIOB setup: + * + * PB0  - PIN0                      (input pullup). + * PB1  - PIN1                      (input pullup). + * PB2  - PIN2                      (input pullup). + * PB3  - PIN3                       (alternate 0). + * PB4  - PIN4                      (input pullup). + * PB5  - PIN5                      (input pullup). + * PB6  - PIN6 LSM303DLHC_SCL   (alternate 4). + * PB7  - PIN7 LSM303DLHC_SDA   (alternate 4). + * PB8  - PIN8                      (input pullup). + * PB9  - PIN9                      (input pullup). + * PB10 - PIN10                     (input pullup). + * PB11 - PIN11                     (input pullup). + * PB12 - PIN12                     (input pullup). + * PB13 - PIN13                     (input pullup). + * PB14 - PIN14                     (input pullup). + * PB15 - PIN15                     (input pullup). + */ +#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | PIN_MODE_INPUT(GPIOB_PIN1) | PIN_MODE_INPUT(GPIOB_PIN2) | PIN_MODE_ALTERNATE(GPIOB_PIN3) | PIN_MODE_INPUT(GPIOB_PIN4) | PIN_MODE_INPUT(GPIOB_PIN5) | PIN_MODE_ALTERNATE(GPIOB_PIN6) | PIN_MODE_OUTPUT(GPIOB_PIN7) | PIN_MODE_INPUT(GPIOB_PIN8) | PIN_MODE_INPUT(GPIOB_PIN9) | PIN_MODE_INPUT(GPIOB_PIN10) | PIN_MODE_INPUT(GPIOB_PIN11) | PIN_MODE_INPUT(GPIOB_PIN12) | PIN_MODE_INPUT(GPIOB_PIN13) | PIN_MODE_INPUT(GPIOB_PIN14) | PIN_MODE_INPUT(GPIOB_PIN15)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | PIN_OTYPE_PUSHPULL(GPIOB_PIN3) | PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | PIN_OTYPE_OPENDRAIN(GPIOB_PIN6) | PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOB_PIN0) | PIN_OSPEED_VERYLOW(GPIOB_PIN1) | PIN_OSPEED_VERYLOW(GPIOB_PIN2) | PIN_OSPEED_HIGH(GPIOB_PIN3) | PIN_OSPEED_VERYLOW(GPIOB_PIN4) | PIN_OSPEED_VERYLOW(GPIOB_PIN5) | PIN_OSPEED_HIGH(GPIOB_PIN6) | PIN_OSPEED_VERYLOW(GPIOB_PIN7) | PIN_OSPEED_VERYLOW(GPIOB_PIN8) | PIN_OSPEED_VERYLOW(GPIOB_PIN9) | PIN_OSPEED_VERYLOW(GPIOB_PIN10) | PIN_OSPEED_VERYLOW(GPIOB_PIN11) | PIN_OSPEED_VERYLOW(GPIOB_PIN12) | PIN_OSPEED_VERYLOW(GPIOB_PIN13) | PIN_OSPEED_VERYLOW(GPIOB_PIN14) | PIN_OSPEED_VERYLOW(GPIOB_PIN15)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | PIN_PUPDR_PULLUP(GPIOB_PIN1) | PIN_PUPDR_PULLUP(GPIOB_PIN2) | PIN_PUPDR_FLOATING(GPIOB_PIN3) | PIN_PUPDR_PULLUP(GPIOB_PIN4) | PIN_PUPDR_PULLUP(GPIOB_PIN5) | PIN_PUPDR_FLOATING(GPIOB_PIN6) | PIN_PUPDR_PULLDOWN(GPIOB_PIN7) | PIN_PUPDR_PULLUP(GPIOB_PIN8) | PIN_PUPDR_PULLUP(GPIOB_PIN9) | PIN_PUPDR_PULLUP(GPIOB_PIN10) | PIN_PUPDR_PULLUP(GPIOB_PIN11) | PIN_PUPDR_PULLUP(GPIOB_PIN12) | PIN_PUPDR_PULLUP(GPIOB_PIN13) | PIN_PUPDR_PULLUP(GPIOB_PIN14) | PIN_PUPDR_PULLUP(GPIOB_PIN15)) +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | PIN_ODR_HIGH(GPIOB_PIN1) | PIN_ODR_HIGH(GPIOB_PIN2) | PIN_ODR_HIGH(GPIOB_PIN3) | PIN_ODR_HIGH(GPIOB_PIN4) | PIN_ODR_HIGH(GPIOB_PIN5) | PIN_ODR_HIGH(GPIOB_PIN6) | PIN_ODR_LOW(GPIOB_PIN7) | PIN_ODR_HIGH(GPIOB_PIN8) | PIN_ODR_HIGH(GPIOB_PIN9) | PIN_ODR_HIGH(GPIOB_PIN10) | PIN_ODR_HIGH(GPIOB_PIN11) | PIN_ODR_HIGH(GPIOB_PIN12) | PIN_ODR_HIGH(GPIOB_PIN13) | PIN_ODR_HIGH(GPIOB_PIN14) | PIN_ODR_HIGH(GPIOB_PIN15)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0) | PIN_AFIO_AF(GPIOB_PIN1, 0) | PIN_AFIO_AF(GPIOB_PIN2, 0) | PIN_AFIO_AF(GPIOB_PIN3, 0) | PIN_AFIO_AF(GPIOB_PIN4, 0) | PIN_AFIO_AF(GPIOB_PIN5, 0) | PIN_AFIO_AF(GPIOB_PIN6, 4) | PIN_AFIO_AF(GPIOB_PIN7, 0)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0) | PIN_AFIO_AF(GPIOB_PIN9, 0) | PIN_AFIO_AF(GPIOB_PIN10, 0) | PIN_AFIO_AF(GPIOB_PIN11, 0) | PIN_AFIO_AF(GPIOB_PIN12, 0) | PIN_AFIO_AF(GPIOB_PIN13, 0) | PIN_AFIO_AF(GPIOB_PIN14, 0) | PIN_AFIO_AF(GPIOB_PIN15, 0)) + +/* + * GPIOC setup: + * + * PC0  - PIN0                      (input pullup). + * PC1  - PIN1                      (input pullup). + * PC2  - PIN2                      (input pullup). + * PC3  - PIN3                      (input pullup). + * PC4  - PIN4                      (input pullup). + * PC5  - PIN5                      (input pullup). + * PC6  - PIN6                      (input pullup). + * PC7  - PIN7                      (input pullup). + * PC8  - PIN8                      (input pullup). + * PC9  - PIN9                      (input pullup). + * PC10 - PIN10                     (input pullup). + * PC11 - PIN11                     (input pullup). + * PC12 - PIN12                     (input pullup). + * PC13 - PIN13                     (input pullup). + * PC14 - PIN14                  (input floating). + * PC15 - PIN15                 (input floating). + */ +#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | PIN_MODE_INPUT(GPIOC_PIN1) | PIN_MODE_INPUT(GPIOC_PIN2) | PIN_MODE_INPUT(GPIOC_PIN3) | PIN_MODE_INPUT(GPIOC_PIN4) | PIN_MODE_INPUT(GPIOC_PIN5) | PIN_MODE_INPUT(GPIOC_PIN6) | PIN_MODE_INPUT(GPIOC_PIN7) | PIN_MODE_INPUT(GPIOC_PIN8) | PIN_MODE_INPUT(GPIOC_PIN9) | PIN_MODE_INPUT(GPIOC_PIN10) | PIN_MODE_INPUT(GPIOC_PIN11) | PIN_MODE_INPUT(GPIOC_PIN12) | PIN_MODE_INPUT(GPIOC_PIN13) | PIN_MODE_INPUT(GPIOC_PIN14) | PIN_MODE_INPUT(GPIOC_PIN15)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | PIN_OTYPE_PUSHPULL(GPIOC_PIN15)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOC_PIN0) | PIN_OSPEED_VERYLOW(GPIOC_PIN1) | PIN_OSPEED_VERYLOW(GPIOC_PIN2) | PIN_OSPEED_VERYLOW(GPIOC_PIN3) | PIN_OSPEED_VERYLOW(GPIOC_PIN4) | PIN_OSPEED_VERYLOW(GPIOC_PIN5) | PIN_OSPEED_VERYLOW(GPIOC_PIN6) | PIN_OSPEED_VERYLOW(GPIOC_PIN7) | PIN_OSPEED_VERYLOW(GPIOC_PIN8) | PIN_OSPEED_VERYLOW(GPIOC_PIN9) | PIN_OSPEED_VERYLOW(GPIOC_PIN10) | PIN_OSPEED_VERYLOW(GPIOC_PIN11) | PIN_OSPEED_VERYLOW(GPIOC_PIN12) | PIN_OSPEED_VERYLOW(GPIOC_PIN13) | PIN_OSPEED_HIGH(GPIOC_PIN14) | PIN_OSPEED_HIGH(GPIOC_PIN15)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | PIN_PUPDR_PULLUP(GPIOC_PIN1) | PIN_PUPDR_PULLUP(GPIOC_PIN2) | PIN_PUPDR_PULLUP(GPIOC_PIN3) | PIN_PUPDR_PULLUP(GPIOC_PIN4) | PIN_PUPDR_PULLUP(GPIOC_PIN5) | PIN_PUPDR_PULLUP(GPIOC_PIN6) | PIN_PUPDR_PULLUP(GPIOC_PIN7) | PIN_PUPDR_PULLUP(GPIOC_PIN8) | PIN_PUPDR_PULLUP(GPIOC_PIN9) | PIN_PUPDR_PULLUP(GPIOC_PIN10) | PIN_PUPDR_PULLUP(GPIOC_PIN11) | PIN_PUPDR_PULLUP(GPIOC_PIN12) | PIN_PUPDR_PULLUP(GPIOC_PIN13) | PIN_PUPDR_FLOATING(GPIOC_PIN14) | PIN_PUPDR_FLOATING(GPIOC_PIN15)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | PIN_ODR_HIGH(GPIOC_PIN1) | PIN_ODR_HIGH(GPIOC_PIN2) | PIN_ODR_HIGH(GPIOC_PIN3) | PIN_ODR_HIGH(GPIOC_PIN4) | PIN_ODR_HIGH(GPIOC_PIN5) | PIN_ODR_HIGH(GPIOC_PIN6) | PIN_ODR_HIGH(GPIOC_PIN7) | PIN_ODR_HIGH(GPIOC_PIN8) | PIN_ODR_HIGH(GPIOC_PIN9) | PIN_ODR_HIGH(GPIOC_PIN10) | PIN_ODR_HIGH(GPIOC_PIN11) | PIN_ODR_HIGH(GPIOC_PIN12) | PIN_ODR_HIGH(GPIOC_PIN13) | PIN_ODR_HIGH(GPIOC_PIN14) | PIN_ODR_HIGH(GPIOC_PIN15)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0) | PIN_AFIO_AF(GPIOC_PIN1, 0) | PIN_AFIO_AF(GPIOC_PIN2, 0) | PIN_AFIO_AF(GPIOC_PIN3, 0) | PIN_AFIO_AF(GPIOC_PIN4, 0) | PIN_AFIO_AF(GPIOC_PIN5, 0) | PIN_AFIO_AF(GPIOC_PIN6, 0) | PIN_AFIO_AF(GPIOC_PIN7, 0)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0) | PIN_AFIO_AF(GPIOC_PIN9, 0) | PIN_AFIO_AF(GPIOC_PIN10, 0) | PIN_AFIO_AF(GPIOC_PIN11, 0) | PIN_AFIO_AF(GPIOC_PIN12, 0) | PIN_AFIO_AF(GPIOC_PIN13, 0) | PIN_AFIO_AF(GPIOC_PIN14, 0) | PIN_AFIO_AF(GPIOC_PIN15, 0)) + +/* + * GPIOD setup: + * + * PD0  - PIN0                      (input pullup). + * PD1  - PIN1                      (input pullup). + * PD2  - PIN2                      (input pullup). + * PD3  - PIN3                      (input pullup). + * PD4  - PIN4                      (input pullup). + * PD5  - PIN5                      (input pullup). + * PD6  - PIN6                      (input pullup). + * PD7  - PIN7                      (input pullup). + * PD8  - PIN8                      (input pullup). + * PD9  - PIN9                      (input pullup). + * PD11 - PIN10                     (input pullup). + * PD11 - PIN11                     (input pullup). + * PD12 - PIN12                     (input pullup). + * PD13 - PIN13                     (input pullup). + * PD14 - PIN14                     (input pullup). + * PD15 - PIN15                     (input pullup). + */ +#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | PIN_MODE_INPUT(GPIOD_PIN1) | PIN_MODE_INPUT(GPIOD_PIN2) | PIN_MODE_INPUT(GPIOD_PIN3) | PIN_MODE_INPUT(GPIOD_PIN4) | PIN_MODE_INPUT(GPIOD_PIN5) | PIN_MODE_INPUT(GPIOD_PIN6) | PIN_MODE_INPUT(GPIOD_PIN7) | PIN_MODE_INPUT(GPIOD_PIN8) | PIN_MODE_INPUT(GPIOD_PIN9) | PIN_MODE_INPUT(GPIOD_PIN10) | PIN_MODE_INPUT(GPIOD_PIN11) | PIN_MODE_INPUT(GPIOD_PIN12) | PIN_MODE_INPUT(GPIOD_PIN13) | PIN_MODE_INPUT(GPIOD_PIN14) | PIN_MODE_INPUT(GPIOD_PIN15)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOD_PIN0) | PIN_OSPEED_VERYLOW(GPIOD_PIN1) | PIN_OSPEED_VERYLOW(GPIOD_PIN2) | PIN_OSPEED_VERYLOW(GPIOD_PIN3) | PIN_OSPEED_VERYLOW(GPIOD_PIN4) | PIN_OSPEED_VERYLOW(GPIOD_PIN5) | PIN_OSPEED_VERYLOW(GPIOD_PIN6) | PIN_OSPEED_VERYLOW(GPIOD_PIN7) | PIN_OSPEED_VERYLOW(GPIOD_PIN8) | PIN_OSPEED_VERYLOW(GPIOD_PIN9) | PIN_OSPEED_VERYLOW(GPIOD_PIN10) | PIN_OSPEED_VERYLOW(GPIOD_PIN11) | PIN_OSPEED_VERYLOW(GPIOD_PIN12) | PIN_OSPEED_VERYLOW(GPIOD_PIN13) | PIN_OSPEED_VERYLOW(GPIOD_PIN14) | PIN_OSPEED_VERYLOW(GPIOD_PIN15)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | PIN_PUPDR_PULLUP(GPIOD_PIN1) | PIN_PUPDR_PULLUP(GPIOD_PIN2) | PIN_PUPDR_PULLUP(GPIOD_PIN3) | PIN_PUPDR_PULLUP(GPIOD_PIN4) | PIN_PUPDR_PULLUP(GPIOD_PIN5) | PIN_PUPDR_PULLUP(GPIOD_PIN6) | PIN_PUPDR_PULLUP(GPIOD_PIN7) | PIN_PUPDR_PULLUP(GPIOD_PIN8) | PIN_PUPDR_PULLUP(GPIOD_PIN9) | PIN_PUPDR_PULLUP(GPIOD_PIN10) | PIN_PUPDR_PULLUP(GPIOD_PIN11) | PIN_PUPDR_PULLUP(GPIOD_PIN12) | PIN_PUPDR_PULLUP(GPIOD_PIN13) | PIN_PUPDR_PULLUP(GPIOD_PIN14) | PIN_PUPDR_PULLUP(GPIOD_PIN15)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | PIN_ODR_HIGH(GPIOD_PIN1) | PIN_ODR_HIGH(GPIOD_PIN2) | PIN_ODR_HIGH(GPIOD_PIN3) | PIN_ODR_HIGH(GPIOD_PIN4) | PIN_ODR_HIGH(GPIOD_PIN5) | PIN_ODR_HIGH(GPIOD_PIN6) | PIN_ODR_HIGH(GPIOD_PIN7) | PIN_ODR_HIGH(GPIOD_PIN8) | PIN_ODR_HIGH(GPIOD_PIN9) | PIN_ODR_HIGH(GPIOD_PIN10) | PIN_ODR_HIGH(GPIOD_PIN11) | PIN_ODR_HIGH(GPIOD_PIN12) | PIN_ODR_HIGH(GPIOD_PIN13) | PIN_ODR_HIGH(GPIOD_PIN14) | PIN_ODR_HIGH(GPIOD_PIN15)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0) | PIN_AFIO_AF(GPIOD_PIN1, 0) | PIN_AFIO_AF(GPIOD_PIN2, 0) | PIN_AFIO_AF(GPIOD_PIN3, 0) | PIN_AFIO_AF(GPIOD_PIN4, 0) | PIN_AFIO_AF(GPIOD_PIN5, 0) | PIN_AFIO_AF(GPIOD_PIN6, 0) | PIN_AFIO_AF(GPIOD_PIN7, 0)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | PIN_AFIO_AF(GPIOD_PIN9, 0) | PIN_AFIO_AF(GPIOD_PIN10, 0) | PIN_AFIO_AF(GPIOD_PIN11, 0) | PIN_AFIO_AF(GPIOD_PIN12, 0) | PIN_AFIO_AF(GPIOD_PIN13, 0) | PIN_AFIO_AF(GPIOD_PIN14, 0) | PIN_AFIO_AF(GPIOD_PIN15, 0)) + +/* + * GPIOE setup: + * + * PE0  - PIN0               (input pullup). + * PE1  - PIN1               (input pullup). + * PE2  - PIN2           (input pullup). + * PE3  - PIN3 L3GD20_CS         (output pushpull maximum). + * PE4  - PIN4           (input pullup). + * PE5  - PIN5           (input pullup). + * PE6  - PIN6                      (input pullup). + * PE7  - PIN7                      (input pullup). + * PE8  - PIN8                 (output pushpull maximum). + * PE9  - PIN9                  (output pushpull maximum). + * PE10 - PIN10               (output pushpull maximum). + * PE11 - PIN11                (output pushpull maximum). + * PE12 - PIN12                 (output pushpull maximum). + * PE13 - PIN13                 (output pushpull maximum). + * PE14 - PIN14               (output pushpull maximum). + * PE15 - PIN15                (output pushpull maximum). + */ +#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | PIN_MODE_INPUT(GPIOE_PIN1) | PIN_MODE_INPUT(GPIOE_PIN2) | PIN_MODE_OUTPUT(GPIOE_PIN3) | PIN_MODE_INPUT(GPIOE_PIN4) | PIN_MODE_INPUT(GPIOE_PIN5) | PIN_MODE_INPUT(GPIOE_PIN6) | PIN_MODE_INPUT(GPIOE_PIN7) | PIN_MODE_OUTPUT(GPIOE_PIN8) | PIN_MODE_OUTPUT(GPIOE_PIN9) | PIN_MODE_OUTPUT(GPIOE_PIN10) | PIN_MODE_OUTPUT(GPIOE_PIN11) | PIN_MODE_OUTPUT(GPIOE_PIN12) | PIN_MODE_OUTPUT(GPIOE_PIN13) | PIN_MODE_OUTPUT(GPIOE_PIN14) | PIN_MODE_OUTPUT(GPIOE_PIN15)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOE_PIN0) | PIN_OSPEED_VERYLOW(GPIOE_PIN1) | PIN_OSPEED_VERYLOW(GPIOE_PIN2) | PIN_OSPEED_HIGH(GPIOE_PIN3) | PIN_OSPEED_VERYLOW(GPIOE_PIN4) | PIN_OSPEED_VERYLOW(GPIOE_PIN5) | PIN_OSPEED_VERYLOW(GPIOE_PIN6) | PIN_OSPEED_VERYLOW(GPIOE_PIN7) | PIN_OSPEED_HIGH(GPIOE_PIN8) | PIN_OSPEED_HIGH(GPIOE_PIN9) | PIN_OSPEED_HIGH(GPIOE_PIN10) | PIN_OSPEED_HIGH(GPIOE_PIN11) | PIN_OSPEED_HIGH(GPIOE_PIN12) | PIN_OSPEED_HIGH(GPIOE_PIN13) | PIN_OSPEED_HIGH(GPIOE_PIN14) | PIN_OSPEED_HIGH(GPIOE_PIN15)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | PIN_PUPDR_PULLUP(GPIOE_PIN1) | PIN_PUPDR_PULLUP(GPIOE_PIN2) | PIN_PUPDR_FLOATING(GPIOE_PIN3) | PIN_PUPDR_PULLUP(GPIOE_PIN4) | PIN_PUPDR_PULLUP(GPIOE_PIN5) | PIN_PUPDR_PULLUP(GPIOE_PIN6) | PIN_PUPDR_PULLUP(GPIOE_PIN7) | PIN_PUPDR_PULLUP(GPIOE_PIN8) | PIN_PUPDR_PULLUP(GPIOE_PIN9) | PIN_PUPDR_PULLUP(GPIOE_PIN10) | PIN_PUPDR_FLOATING(GPIOE_PIN11) | PIN_PUPDR_PULLUP(GPIOE_PIN12) | PIN_PUPDR_FLOATING(GPIOE_PIN13) | PIN_PUPDR_FLOATING(GPIOE_PIN14) | PIN_PUPDR_FLOATING(GPIOE_PIN15)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | PIN_ODR_HIGH(GPIOE_PIN1) | PIN_ODR_HIGH(GPIOE_PIN2) | PIN_ODR_HIGH(GPIOE_PIN3) | PIN_ODR_HIGH(GPIOE_PIN4) | PIN_ODR_HIGH(GPIOE_PIN5) | PIN_ODR_HIGH(GPIOE_PIN6) | PIN_ODR_HIGH(GPIOE_PIN7) | PIN_ODR_LOW(GPIOE_PIN8) | PIN_ODR_LOW(GPIOE_PIN9) | PIN_ODR_LOW(GPIOE_PIN10) | PIN_ODR_LOW(GPIOE_PIN11) | PIN_ODR_LOW(GPIOE_PIN12) | PIN_ODR_LOW(GPIOE_PIN13) | PIN_ODR_LOW(GPIOE_PIN14) | PIN_ODR_LOW(GPIOE_PIN15)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0) | PIN_AFIO_AF(GPIOE_PIN1, 0) | PIN_AFIO_AF(GPIOE_PIN2, 0) | PIN_AFIO_AF(GPIOE_PIN3, 0) | PIN_AFIO_AF(GPIOE_PIN4, 0) | PIN_AFIO_AF(GPIOE_PIN5, 0) | PIN_AFIO_AF(GPIOE_PIN6, 0) | PIN_AFIO_AF(GPIOE_PIN7, 0)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0) | PIN_AFIO_AF(GPIOE_PIN9, 0) | PIN_AFIO_AF(GPIOE_PIN10, 0) | PIN_AFIO_AF(GPIOE_PIN11, 0) | PIN_AFIO_AF(GPIOE_PIN12, 0) | PIN_AFIO_AF(GPIOE_PIN13, 0) | PIN_AFIO_AF(GPIOE_PIN14, 0) | PIN_AFIO_AF(GPIOE_PIN15, 0)) + +/* + * GPIOF setup: + * + * PF0  - I2C2_SDA                    (input floating). + * PF1  - I2C2_SCL                   (input floating). + * PF2  - PIN2                      (input pullup). + * PF3  - PIN3                      (input pullup). + * PF4  - PIN4                      (input pullup). + * PF5  - PIN5                      (input pullup). + * PF6  - PIN6                      (input pullup). + * PF7  - PIN7                      (input pullup). + * PF8  - PIN8                      (input pullup). + * PF9  - PIN9                      (input pullup). + * PF10 - PIN10                     (input pullup). + * PF11 - PIN11                     (input pullup). + * PF12 - PIN12                     (input pullup). + * PF13 - PIN13                     (input pullup). + * PF14 - PIN14                     (input pullup). + * PF15 - PIN15                     (input pullup). + */ +#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_I2C2_SDA) | PIN_MODE_INPUT(GPIOF_I2C2_SCL) | PIN_MODE_INPUT(GPIOF_PIN2) | PIN_MODE_INPUT(GPIOF_PIN3) | PIN_MODE_INPUT(GPIOF_PIN4) | PIN_MODE_INPUT(GPIOF_PIN5) | PIN_MODE_INPUT(GPIOF_PIN6) | PIN_MODE_INPUT(GPIOF_PIN7) | PIN_MODE_INPUT(GPIOF_PIN8) | PIN_MODE_INPUT(GPIOF_PIN9) | PIN_MODE_INPUT(GPIOF_PIN10) | PIN_MODE_INPUT(GPIOF_PIN11) | PIN_MODE_INPUT(GPIOF_PIN12) | PIN_MODE_INPUT(GPIOF_PIN13) | PIN_MODE_INPUT(GPIOF_PIN14) | PIN_MODE_INPUT(GPIOF_PIN15)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_I2C2_SDA) | PIN_OTYPE_PUSHPULL(GPIOF_I2C2_SCL) | PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_I2C2_SDA) | PIN_OSPEED_HIGH(GPIOF_I2C2_SCL) | PIN_OSPEED_VERYLOW(GPIOF_PIN2) | PIN_OSPEED_VERYLOW(GPIOF_PIN3) | PIN_OSPEED_VERYLOW(GPIOF_PIN4) | PIN_OSPEED_VERYLOW(GPIOF_PIN5) | PIN_OSPEED_VERYLOW(GPIOF_PIN6) | PIN_OSPEED_VERYLOW(GPIOF_PIN7) | PIN_OSPEED_VERYLOW(GPIOF_PIN8) | PIN_OSPEED_VERYLOW(GPIOF_PIN9) | PIN_OSPEED_VERYLOW(GPIOF_PIN10) | PIN_OSPEED_VERYLOW(GPIOF_PIN11) | PIN_OSPEED_VERYLOW(GPIOF_PIN12) | PIN_OSPEED_VERYLOW(GPIOF_PIN13) | PIN_OSPEED_VERYLOW(GPIOF_PIN14) | PIN_OSPEED_VERYLOW(GPIOF_PIN15)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_I2C2_SDA) | PIN_PUPDR_FLOATING(GPIOF_I2C2_SCL) | PIN_PUPDR_PULLUP(GPIOF_PIN2) | PIN_PUPDR_PULLUP(GPIOF_PIN3) | PIN_PUPDR_PULLUP(GPIOF_PIN4) | PIN_PUPDR_PULLUP(GPIOF_PIN5) | PIN_PUPDR_PULLUP(GPIOF_PIN6) | PIN_PUPDR_PULLUP(GPIOF_PIN7) | PIN_PUPDR_PULLUP(GPIOF_PIN8) | PIN_PUPDR_PULLUP(GPIOF_PIN9) | PIN_PUPDR_PULLUP(GPIOF_PIN10) | PIN_PUPDR_PULLUP(GPIOF_PIN11) | PIN_PUPDR_PULLUP(GPIOF_PIN12) | PIN_PUPDR_PULLUP(GPIOF_PIN13) | PIN_PUPDR_PULLUP(GPIOF_PIN14) | PIN_PUPDR_PULLUP(GPIOF_PIN15)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_I2C2_SDA) | PIN_ODR_HIGH(GPIOF_I2C2_SCL) | PIN_ODR_HIGH(GPIOF_PIN2) | PIN_ODR_HIGH(GPIOF_PIN3) | PIN_ODR_HIGH(GPIOF_PIN4) | PIN_ODR_HIGH(GPIOF_PIN5) | PIN_ODR_HIGH(GPIOF_PIN6) | PIN_ODR_HIGH(GPIOF_PIN7) | PIN_ODR_HIGH(GPIOF_PIN8) | PIN_ODR_HIGH(GPIOF_PIN9) | PIN_ODR_HIGH(GPIOF_PIN10) | PIN_ODR_HIGH(GPIOF_PIN11) | PIN_ODR_HIGH(GPIOF_PIN12) | PIN_ODR_HIGH(GPIOF_PIN13) | PIN_ODR_HIGH(GPIOF_PIN14) | PIN_ODR_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_I2C2_SDA, 0) | PIN_AFIO_AF(GPIOF_I2C2_SCL, 0) | PIN_AFIO_AF(GPIOF_PIN2, 0) | PIN_AFIO_AF(GPIOF_PIN3, 0) | PIN_AFIO_AF(GPIOF_PIN4, 0) | PIN_AFIO_AF(GPIOF_PIN5, 0) | PIN_AFIO_AF(GPIOF_PIN6, 0) | PIN_AFIO_AF(GPIOF_PIN7, 0)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | PIN_AFIO_AF(GPIOF_PIN9, 0) | PIN_AFIO_AF(GPIOF_PIN10, 0) | PIN_AFIO_AF(GPIOF_PIN11, 0) | PIN_AFIO_AF(GPIOF_PIN12, 0) | PIN_AFIO_AF(GPIOF_PIN13, 0) | PIN_AFIO_AF(GPIOF_PIN14, 0) | PIN_AFIO_AF(GPIOF_PIN15, 0)) + +/* + * GPIOG setup: + * + * PG0  - PIN0                      (input pullup). + * PG1  - PIN1                      (input pullup). + * PG2  - PIN2                      (input pullup). + * PG3  - PIN3                      (input pullup). + * PG4  - PIN4                      (input pullup). + * PG5  - PIN5                      (input pullup). + * PG6  - PIN6                      (input pullup). + * PG7  - PIN7                      (input pullup). + * PG8  - PIN8                      (input pullup). + * PG9  - PIN9                      (input pullup). + * PG10 - PIN10                     (input pullup). + * PG11 - PIN11                     (input pullup). + * PG12 - PIN12                     (input pullup). + * PG13 - PIN13                     (input pullup). + * PG14 - PIN14                     (input pullup). + * PG15 - PIN15                     (input pullup). + */ +#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | PIN_MODE_INPUT(GPIOG_PIN1) | PIN_MODE_INPUT(GPIOG_PIN2) | PIN_MODE_INPUT(GPIOG_PIN3) | PIN_MODE_INPUT(GPIOG_PIN4) | PIN_MODE_INPUT(GPIOG_PIN5) | PIN_MODE_INPUT(GPIOG_PIN6) | PIN_MODE_INPUT(GPIOG_PIN7) | PIN_MODE_INPUT(GPIOG_PIN8) | PIN_MODE_INPUT(GPIOG_PIN9) | PIN_MODE_INPUT(GPIOG_PIN10) | PIN_MODE_INPUT(GPIOG_PIN11) | PIN_MODE_INPUT(GPIOG_PIN12) | PIN_MODE_INPUT(GPIOG_PIN13) | PIN_MODE_INPUT(GPIOG_PIN14) | PIN_MODE_INPUT(GPIOG_PIN15)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOG_PIN0) | PIN_OSPEED_VERYLOW(GPIOG_PIN1) | PIN_OSPEED_VERYLOW(GPIOG_PIN2) | PIN_OSPEED_VERYLOW(GPIOG_PIN3) | PIN_OSPEED_VERYLOW(GPIOG_PIN4) | PIN_OSPEED_VERYLOW(GPIOG_PIN5) | PIN_OSPEED_VERYLOW(GPIOG_PIN6) | PIN_OSPEED_VERYLOW(GPIOG_PIN7) | PIN_OSPEED_VERYLOW(GPIOG_PIN8) | PIN_OSPEED_VERYLOW(GPIOG_PIN9) | PIN_OSPEED_VERYLOW(GPIOG_PIN10) | PIN_OSPEED_VERYLOW(GPIOG_PIN11) | PIN_OSPEED_VERYLOW(GPIOG_PIN12) | PIN_OSPEED_VERYLOW(GPIOG_PIN13) | PIN_OSPEED_VERYLOW(GPIOG_PIN14) | PIN_OSPEED_VERYLOW(GPIOG_PIN15)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLUP(GPIOG_PIN0) | PIN_PUPDR_PULLUP(GPIOG_PIN1) | PIN_PUPDR_PULLUP(GPIOG_PIN2) | PIN_PUPDR_PULLUP(GPIOG_PIN3) | PIN_PUPDR_PULLUP(GPIOG_PIN4) | PIN_PUPDR_PULLUP(GPIOG_PIN5) | PIN_PUPDR_PULLUP(GPIOG_PIN6) | PIN_PUPDR_PULLUP(GPIOG_PIN7) | PIN_PUPDR_PULLUP(GPIOG_PIN8) | PIN_PUPDR_PULLUP(GPIOG_PIN9) | PIN_PUPDR_PULLUP(GPIOG_PIN10) | PIN_PUPDR_PULLUP(GPIOG_PIN11) | PIN_PUPDR_PULLUP(GPIOG_PIN12) | PIN_PUPDR_PULLUP(GPIOG_PIN13) | PIN_PUPDR_PULLUP(GPIOG_PIN14) | PIN_PUPDR_PULLUP(GPIOG_PIN15)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | PIN_ODR_HIGH(GPIOG_PIN1) | PIN_ODR_HIGH(GPIOG_PIN2) | PIN_ODR_HIGH(GPIOG_PIN3) | PIN_ODR_HIGH(GPIOG_PIN4) | PIN_ODR_HIGH(GPIOG_PIN5) | PIN_ODR_HIGH(GPIOG_PIN6) | PIN_ODR_HIGH(GPIOG_PIN7) | PIN_ODR_HIGH(GPIOG_PIN8) | PIN_ODR_HIGH(GPIOG_PIN9) | PIN_ODR_HIGH(GPIOG_PIN10) | PIN_ODR_HIGH(GPIOG_PIN11) | PIN_ODR_HIGH(GPIOG_PIN12) | PIN_ODR_HIGH(GPIOG_PIN13) | PIN_ODR_HIGH(GPIOG_PIN14) | PIN_ODR_HIGH(GPIOG_PIN15)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0) | PIN_AFIO_AF(GPIOG_PIN1, 0) | PIN_AFIO_AF(GPIOG_PIN2, 0) | PIN_AFIO_AF(GPIOG_PIN3, 0) | PIN_AFIO_AF(GPIOG_PIN4, 0) | PIN_AFIO_AF(GPIOG_PIN5, 0) | PIN_AFIO_AF(GPIOG_PIN6, 0) | PIN_AFIO_AF(GPIOG_PIN7, 0)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0) | PIN_AFIO_AF(GPIOG_PIN9, 0) | PIN_AFIO_AF(GPIOG_PIN10, 0) | PIN_AFIO_AF(GPIOG_PIN11, 0) | PIN_AFIO_AF(GPIOG_PIN12, 0) | PIN_AFIO_AF(GPIOG_PIN13, 0) | PIN_AFIO_AF(GPIOG_PIN14, 0) | PIN_AFIO_AF(GPIOG_PIN15, 0)) + +/* + * GPIOH setup: + * + * PH0  - PIN0                      (input pullup). + * PH1  - PIN1                      (input pullup). + * PH2  - PIN2                      (input pullup). + * PH3  - PIN3                      (input pullup). + * PH4  - PIN4                      (input pullup). + * PH5  - PIN5                      (input pullup). + * PH6  - PIN6                      (input pullup). + * PH7  - PIN7                      (input pullup). + * PH8  - PIN8                      (input pullup). + * PH9  - PIN9                      (input pullup). + * PH10 - PIN10                     (input pullup). + * PH11 - PIN11                     (input pullup). + * PH12 - PIN12                     (input pullup). + * PH13 - PIN13                     (input pullup). + * PH14 - PIN14                     (input pullup). + * PH15 - PIN15                     (input pullup). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_PIN0) | PIN_MODE_INPUT(GPIOH_PIN1) | PIN_MODE_INPUT(GPIOH_PIN2) | PIN_MODE_INPUT(GPIOH_PIN3) | PIN_MODE_INPUT(GPIOH_PIN4) | PIN_MODE_INPUT(GPIOH_PIN5) | PIN_MODE_INPUT(GPIOH_PIN6) | PIN_MODE_INPUT(GPIOH_PIN7) | PIN_MODE_INPUT(GPIOH_PIN8) | PIN_MODE_INPUT(GPIOH_PIN9) | PIN_MODE_INPUT(GPIOH_PIN10) | PIN_MODE_INPUT(GPIOH_PIN11) | PIN_MODE_INPUT(GPIOH_PIN12) | PIN_MODE_INPUT(GPIOH_PIN13) | PIN_MODE_INPUT(GPIOH_PIN14) | PIN_MODE_INPUT(GPIOH_PIN15)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_PIN0) | PIN_OTYPE_PUSHPULL(GPIOH_PIN1) | PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOH_PIN0) | PIN_OSPEED_VERYLOW(GPIOH_PIN1) | PIN_OSPEED_VERYLOW(GPIOH_PIN2) | PIN_OSPEED_VERYLOW(GPIOH_PIN3) | PIN_OSPEED_VERYLOW(GPIOH_PIN4) | PIN_OSPEED_VERYLOW(GPIOH_PIN5) | PIN_OSPEED_VERYLOW(GPIOH_PIN6) | PIN_OSPEED_VERYLOW(GPIOH_PIN7) | PIN_OSPEED_VERYLOW(GPIOH_PIN8) | PIN_OSPEED_VERYLOW(GPIOH_PIN9) | PIN_OSPEED_VERYLOW(GPIOH_PIN10) | PIN_OSPEED_VERYLOW(GPIOH_PIN11) | PIN_OSPEED_VERYLOW(GPIOH_PIN12) | PIN_OSPEED_VERYLOW(GPIOH_PIN13) | PIN_OSPEED_VERYLOW(GPIOH_PIN14) | PIN_OSPEED_VERYLOW(GPIOH_PIN15)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_PULLUP(GPIOH_PIN0) | PIN_PUPDR_PULLUP(GPIOH_PIN1) | PIN_PUPDR_PULLUP(GPIOH_PIN2) | PIN_PUPDR_PULLUP(GPIOH_PIN3) | PIN_PUPDR_PULLUP(GPIOH_PIN4) | PIN_PUPDR_PULLUP(GPIOH_PIN5) | PIN_PUPDR_PULLUP(GPIOH_PIN6) | PIN_PUPDR_PULLUP(GPIOH_PIN7) | PIN_PUPDR_PULLUP(GPIOH_PIN8) | PIN_PUPDR_PULLUP(GPIOH_PIN9) | PIN_PUPDR_PULLUP(GPIOH_PIN10) | PIN_PUPDR_PULLUP(GPIOH_PIN11) | PIN_PUPDR_PULLUP(GPIOH_PIN12) | PIN_PUPDR_PULLUP(GPIOH_PIN13) | PIN_PUPDR_PULLUP(GPIOH_PIN14) | PIN_PUPDR_PULLUP(GPIOH_PIN15)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_PIN0) | PIN_ODR_HIGH(GPIOH_PIN1) | PIN_ODR_HIGH(GPIOH_PIN2) | PIN_ODR_HIGH(GPIOH_PIN3) | PIN_ODR_HIGH(GPIOH_PIN4) | PIN_ODR_HIGH(GPIOH_PIN5) | PIN_ODR_HIGH(GPIOH_PIN6) | PIN_ODR_HIGH(GPIOH_PIN7) | PIN_ODR_HIGH(GPIOH_PIN8) | PIN_ODR_HIGH(GPIOH_PIN9) | PIN_ODR_HIGH(GPIOH_PIN10) | PIN_ODR_HIGH(GPIOH_PIN11) | PIN_ODR_HIGH(GPIOH_PIN12) | PIN_ODR_HIGH(GPIOH_PIN13) | PIN_ODR_HIGH(GPIOH_PIN14) | PIN_ODR_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_PIN0, 0) | PIN_AFIO_AF(GPIOH_PIN1, 0) | PIN_AFIO_AF(GPIOH_PIN2, 0) | PIN_AFIO_AF(GPIOH_PIN3, 0) | PIN_AFIO_AF(GPIOH_PIN4, 0) | PIN_AFIO_AF(GPIOH_PIN5, 0) | PIN_AFIO_AF(GPIOH_PIN6, 0) | PIN_AFIO_AF(GPIOH_PIN7, 0)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0) | PIN_AFIO_AF(GPIOH_PIN9, 0) | PIN_AFIO_AF(GPIOH_PIN10, 0) | PIN_AFIO_AF(GPIOH_PIN11, 0) | PIN_AFIO_AF(GPIOH_PIN12, 0) | PIN_AFIO_AF(GPIOH_PIN13, 0) | PIN_AFIO_AF(GPIOH_PIN14, 0) | PIN_AFIO_AF(GPIOH_PIN15, 0)) + +/* + * USB bus activation macro, required by the USB driver. + */ +// #define usb_lld_connect_bus(usbp) +#define usb_lld_connect_bus(usbp) (palSetPadMode(GPIOA, GPIOA_USB_DP, PAL_MODE_ALTERNATE(14))) +// #define usb_lld_connect_bus(usbp) palSetPadMode(GPIOA, 12, PAL_MODE_INPUT) +/* + * USB bus de-activation macro, required by the USB driver. + */ +// #define usb_lld_disconnect_bus(usbp) +#define usb_lld_disconnect_bus(usbp)                                \ +    (palSetPadMode(GPIOA, GPIOA_USB_DP, PAL_MODE_OUTPUT_PUSHPULL)); \ +    palClearPad(GPIOA, GPIOA_USB_DP) +// #define usb_lld_disconnect_bus(usbp) palSetPadMode(GPIOA, 12, PAL_MODE_OUTPUT_PUSHPULL); palClearPad(GPIOA, 12) + +#if !defined(_FROM_ASM_) +#    ifdef __cplusplus +extern "C" { +#    endif +void boardInit(void); +#    ifdef __cplusplus +} +#    endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/platforms/chibios/GENERIC_STM32_F303XC/board/board.mk b/platforms/chibios/GENERIC_STM32_F303XC/board/board.mk new file mode 100644 index 0000000000..842e335905 --- /dev/null +++ b/platforms/chibios/GENERIC_STM32_F303XC/board/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = $(BOARD_PATH)/board/board.c + +# Required include directories +BOARDINC = $(BOARD_PATH)/board + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC  += $(BOARDINC) diff --git a/platforms/chibios/GENERIC_STM32_F303XC/configs/bootloader_defs.h b/platforms/chibios/GENERIC_STM32_F303XC/configs/bootloader_defs.h new file mode 100644 index 0000000000..3b0e9d20a6 --- /dev/null +++ b/platforms/chibios/GENERIC_STM32_F303XC/configs/bootloader_defs.h @@ -0,0 +1,7 @@ +/* Address for jumping to bootloader on STM32 chips. */ +/* It is chip dependent, the correct number can be looked up here: + * http://www.st.com/web/en/resource/technical/document/application_note/CD00167594.pdf + * This also requires a patch to chibios: + *  <tmk_dir>/tmk_core/tool/chibios/ch-bootloader-jump.patch + */ +#define STM32_BOOTLOADER_ADDRESS 0x1FFFD800 diff --git a/platforms/chibios/GENERIC_STM32_F303XC/configs/chconf.h b/platforms/chibios/GENERIC_STM32_F303XC/configs/chconf.h new file mode 100644 index 0000000000..aac3303705 --- /dev/null +++ b/platforms/chibios/GENERIC_STM32_F303XC/configs/chconf.h @@ -0,0 +1,714 @@ +/* +    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + +    Licensed under the Apache License, Version 2.0 (the "License"); +    you may not use this file except in compliance with the License. +    You may obtain a copy of the License at + +        http://www.apache.org/licenses/LICENSE-2.0 + +    Unless required by applicable law or agreed to in writing, software +    distributed under the License is distributed on an "AS IS" BASIS, +    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +    See the License for the specific language governing permissions and +    limitations under the License. +*/ + +/** + * @file    rt/templates/chconf.h + * @brief   Configuration file template. + * @details A copy of this file must be placed in each project directory, it + *          contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_6_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief   System time counter resolution. + * @note    Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION                32 +#endif + +/** + * @brief   System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + *          setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY                 100000 +#endif + +/** + * @brief   Time intervals data size. + * @note    Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE               32 +#endif + +/** + * @brief   Time types data size. + * @note    Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE              32 +#endif + +/** + * @brief   Time delta constant for the tick-less mode. + * @note    If this value is zero then the system uses the classic + *          periodic tick. This value represents the minimum number + *          of ticks that is safe to specify in a timeout directive. + *          The value one is not valid, timeouts are rounded up to + *          this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA                 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief   Round robin interval. + * @details This constant is the number of system ticks allowed for the + *          threads before preemption occurs. Setting this value to zero + *          disables the preemption for threads with equal priority and the + *          round robin becomes cooperative. Note that higher priority + *          threads can still preempt, the kernel is always preemptive. + * @note    Disabling the round robin preemption makes the kernel more compact + *          and generally faster. + * @note    The round robin preemption is not supported in tickless mode and + *          must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM                 0 +#endif + +/** + * @brief   Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + *          then the whole available RAM is used. The core memory is made + *          available to the heap allocator and/or can be used directly through + *          the simplified core memory allocator. + * + * @note    In order to let the OS manage the whole RAM the linker script must + *          provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note    Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE                 0 +#endif + +/** + * @brief   Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + *          does not spawn the idle thread. The application @p main() + *          function becomes the idle thread and must implement an + *          infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD               FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief   OS optimization. + * @details If enabled then time efficient rather than space efficient code + *          is used when two possible implementations exist. + * + * @note    This is not related to the compiler optimization options. + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED               TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief   Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + *          the kernel. + * + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM                       TRUE +#endif + +/** + * @brief   Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY                 TRUE +#endif + +/** + * @brief   Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + *          the kernel. + * + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT                 TRUE +#endif + +/** + * @brief   Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES               TRUE +#endif + +/** + * @brief   Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + *          priority rather than in FIFO order. + * + * @note    The default is @p FALSE. Enable this if you have special + *          requirements. + * @note    Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY      FALSE +#endif + +/** + * @brief   Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES                  TRUE +#endif + +/** + * @brief   Enables recursive behavior on mutexes. + * @note    Recursive mutexes are heavier and have an increased + *          memory footprint. + * + * @note    The default is @p FALSE. + * @note    Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE        FALSE +#endif + +/** + * @brief   Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + *          in the kernel. + * + * @note    The default is @p TRUE. + * @note    Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS                 TRUE +#endif + +/** + * @brief   Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + *          specification are included in the kernel. + * + * @note    The default is @p TRUE. + * @note    Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT         TRUE +#endif + +/** + * @brief   Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS                   TRUE +#endif + +/** + * @brief   Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + *          are included in the kernel. + * + * @note    The default is @p TRUE. + * @note    Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT           TRUE +#endif + +/** + * @brief   Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + *          in the kernel. + * + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES                 TRUE +#endif + +/** + * @brief   Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + *          FIFO order. + * + * @note    The default is @p FALSE. Enable this if you have special + *          requirements. + * @note    Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY        TRUE +#endif + +/** + * @brief   Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + *          included in the kernel. + * + * @note    The default is @p TRUE. + * @note    Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES                TRUE +#endif + +/** + * @brief   Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + *          in the kernel. + * + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE                  TRUE +#endif + +/** + * @brief   Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + *          in the kernel. + * + * @note    The default is @p TRUE. + * @note    Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + *          @p CH_CFG_USE_SEMAPHORES. + * @note    Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP                     TRUE +#endif + +/** + * @brief   Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + *          in the kernel. + * + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS                 TRUE +#endif + +/** + * @brief   Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + *          in the kernel. + * + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS                TRUE +#endif + +/** + * @brief   Pipes APIs. + * @details If enabled then the pipes APIs are included + *          in the kernel. + * + * @note    The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES                    TRUE +#endif + +/** + * @brief   Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + *          in the kernel. + * + * @note    The default is @p TRUE. + * @note    Requires @p CH_CFG_USE_WAITEXIT. + * @note    Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC                  TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief   Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + *          kernel. + * + * @note    The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY                  TRUE +#endif + +/** + * @brief   Maximum length for object names. + * @details If the specified length is zero then the name is stored by + *          pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH     8 +#endif + +/** + * @brief   Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY     TRUE +#endif + +/** + * @brief   Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS      TRUE +#endif + +/** + * @brief   Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES           TRUE +#endif + +/** + * @brief   Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES            TRUE +#endif + +/** + * @brief   Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS            TRUE +#endif + +/** + * @brief   Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES                TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief   Debug option, kernel statistics. + * + * @note    The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS                   FALSE +#endif + +/** + * @brief   Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + *          at runtime. + * + * @note    The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK           FALSE +#endif + +/** + * @brief   Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + *          parameters are activated. + * + * @note    The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS                FALSE +#endif + +/** + * @brief   Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + *          activated. This includes consistency checks inside the kernel, + *          runtime anomalies and port-defined checks. + * + * @note    The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS               FALSE +#endif + +/** + * @brief   Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note    The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK                   CH_DBG_TRACE_MASK_DISABLED +#endif + +/** + * @brief   Trace buffer entries. + * @note    The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + *          different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE            128 +#endif + +/** + * @brief   Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note    The default is @p FALSE. + * @note    The stack check is performed in a architecture/port dependent way. + *          It may not be implemented or some ports. + * @note    The default failure mode is to halt the system with the global + *          @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK           TRUE +#endif + +/** + * @brief   Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + *          value when a thread is created. This can be useful for the + *          runtime measurement of the used stack. + * + * @note    The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS                 FALSE +#endif + +/** + * @brief   Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + *          counts the system ticks occurred while executing the thread. + * + * @note    The default is @p FALSE. + * @note    This debug option is not currently compatible with the + *          tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING            FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief   System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS                                          \ +  /* Add threads custom fields here.*/ + +/** + * @brief   System initialization hook. + * @details User initialization code added to the @p chSysInit() function + *          just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() {                                         \ +  /* Add threads initialization code here.*/                                \ +} + +/** + * @brief   Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS                                          \ +  /* Add threads custom fields here.*/ + +/** + * @brief   Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note    It is invoked from within @p _thread_init() and implicitly from all + *          the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) {                                       \ +  /* Add threads initialization code here.*/                                \ +} + +/** + * @brief   Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) {                                       \ +  /* Add threads finalization code here.*/                                  \ +} + +/** + * @brief   Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) {                              \ +  /* Context switch code here.*/                                            \ +} + +/** + * @brief   ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() {                                        \ +  /* IRQ prologue code here.*/                                              \ +} + +/** + * @brief   ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() {                                        \ +  /* IRQ epilogue code here.*/                                              \ +} + +/** + * @brief   Idle thread enter hook. + * @note    This hook is invoked within a critical zone, no OS functions + *          should be invoked from here. + * @note    This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() {                                          \ +  /* Idle-enter code here.*/                                                \ +} + +/** + * @brief   Idle thread leave hook. + * @note    This hook is invoked within a critical zone, no OS functions + *          should be invoked from here. + * @note    This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() {                                          \ +  /* Idle-leave code here.*/                                                \ +} + +/** + * @brief   Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() {                                           \ +  /* Idle loop code here.*/                                                 \ +} + +/** + * @brief   System tick event hook. + * @details This hook is invoked in the system tick handler immediately + *          after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() {                                         \ +  /* System tick event code here.*/                                         \ +} + +/** + * @brief   System halt hook. + * @details This hook is invoked in case to a system halting error before + *          the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) {                                   \ +  /* System halt code here.*/                                               \ +} + +/** + * @brief   Trace hook. + * @details This hook is invoked each time a new record is written in the + *          trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) {                                            \ +  /* Trace code here.*/                                                     \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h).    */ +/*===========================================================================*/ + +#endif  /* CHCONF_H */ + +/** @} */ diff --git a/platforms/chibios/GENERIC_STM32_F303XC/configs/halconf.h b/platforms/chibios/GENERIC_STM32_F303XC/configs/halconf.h new file mode 100644 index 0000000000..6b48e289f9 --- /dev/null +++ b/platforms/chibios/GENERIC_STM32_F303XC/configs/halconf.h @@ -0,0 +1,525 @@ +/* +    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + +    Licensed under the Apache License, Version 2.0 (the "License"); +    you may not use this file except in compliance with the License. +    You may obtain a copy of the License at + +        http://www.apache.org/licenses/LICENSE-2.0 + +    Unless required by applicable law or agreed to in writing, software +    distributed under the License is distributed on an "AS IS" BASIS, +    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +    See the License for the specific language governing permissions and +    limitations under the License. +*/ + +/** + * @file    templates/halconf.h + * @brief   HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + *          various device drivers from your application. You may also use + *          this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_7_0_ + +#include "mcuconf.h" + +/** + * @brief   Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL                         TRUE +#endif + +/** + * @brief   Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC                         FALSE +#endif + +/** + * @brief   Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN                         FALSE +#endif + +/** + * @brief   Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY                         FALSE +#endif + +/** + * @brief   Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC                         TRUE +#endif + +/** + * @brief   Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT                         TRUE +#endif + +/** + * @brief   Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C                         TRUE +#endif + +/** + * @brief   Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S                         FALSE +#endif + +/** + * @brief   Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU                         FALSE +#endif + +/** + * @brief   Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC                         FALSE +#endif + +/** + * @brief   Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI                     FALSE +#endif + +/** + * @brief   Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM                         TRUE +#endif + +/** + * @brief   Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC                         FALSE +#endif + +/** + * @brief   Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC                         FALSE +#endif + +/** + * @brief   Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL                      FALSE +#endif + +/** + * @brief   Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB                  TRUE +#endif + +/** + * @brief   Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO                         FALSE +#endif + +/** + * @brief   Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI                         TRUE +#endif + +/** + * @brief   Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG                        FALSE +#endif + +/** + * @brief   Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART                        FALSE +#endif + +/** + * @brief   Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB                         TRUE +#endif + +/** + * @brief   Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG                         FALSE +#endif + +/** + * @brief   Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI                        FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings.                                              */ +/*===========================================================================*/ + +/** + * @brief   Enables synchronous APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS                   TRUE +#endif + +/** + * @brief   Enables synchronous APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT                        TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings.                                              */ +/*===========================================================================*/ + +/** + * @brief   Enables synchronous APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT                        TRUE +#endif + +/** + * @brief   Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION            TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings.                                              */ +/*===========================================================================*/ + +/** + * @brief   Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE                  TRUE +#endif + +/** + * @brief   Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS           FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings.                                              */ +/*===========================================================================*/ + +/** + * @brief   Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + *          implementation for algorithms not supported by the underlying + *          hardware. + * @note    Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK                FALSE +#endif + +/** + * @brief   Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK            FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings.                                              */ +/*===========================================================================*/ + +/** + * @brief   Enables synchronous APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT                        TRUE +#endif + +/** + * @brief   Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION            TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings.                                              */ +/*===========================================================================*/ + +/** + * @brief   Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION            TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings.                                              */ +/*===========================================================================*/ + +/** + * @brief   Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY                   FALSE +#endif + +/** + * @brief   Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS                      TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings.                                          */ +/*===========================================================================*/ + +/** + * @brief   Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + *          routines releasing some extra CPU time for the threads with + *          lower priority, this may slow down the driver a bit however. + *          This option is recommended also if the SPI driver does not + *          use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING                    TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings.                                              */ +/*===========================================================================*/ + +/** + * @brief   Number of initialization attempts before rejecting the card. + * @note    Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY                      100 +#endif + +/** + * @brief   Include support for MMC cards. + * @note    MMC support is not yet implemented so this option must be kept + *          at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT                     FALSE +#endif + +/** + * @brief   Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + *          routines releasing some extra CPU time for the threads with + *          lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING                    TRUE +#endif + +/** + * @brief   OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20                    0x50FF8000U +#endif + +/** + * @brief   OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR                        0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings.                                           */ +/*===========================================================================*/ + +/** + * @brief   Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + *          default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE              38400 +#endif + +/** + * @brief   Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + *          buffers depending on the requirements of your application. + * @note    The default is 16 bytes for both the transmission and receive + *          buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE                 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting.                                        */ +/*===========================================================================*/ + +/** + * @brief   Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + *          the USB data endpoint maximum packet size. + * @note    The default is 256 bytes for both the transmission and receive + *          buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE             1 +#endif + +/** + * @brief   Serial over USB number of buffers. + * @note    The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER           2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings.                                              */ +/*===========================================================================*/ + +/** + * @brief   Enables synchronous APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT                        TRUE +#endif + +/** + * @brief   Enables circular transfers APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR                    FALSE +#endif + + +/** + * @brief   Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION            TRUE +#endif + +/** + * @brief   Handling method for SPI CS line. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE                     SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings.                                             */ +/*===========================================================================*/ + +/** + * @brief   Enables synchronous APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT                       FALSE +#endif + +/** + * @brief   Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION           FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings.                                              */ +/*===========================================================================*/ + +/** + * @brief   Enables synchronous APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT                        TRUE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings.                                             */ +/*===========================================================================*/ + +/** + * @brief   Enables synchronous APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT                       TRUE +#endif + +/** + * @brief   Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note    Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION           TRUE +#endif + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/platforms/chibios/GENERIC_STM32_F303XC/configs/mcuconf.h b/platforms/chibios/GENERIC_STM32_F303XC/configs/mcuconf.h new file mode 100644 index 0000000000..3b15883485 --- /dev/null +++ b/platforms/chibios/GENERIC_STM32_F303XC/configs/mcuconf.h @@ -0,0 +1,273 @@ +/* +    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + +    Licensed under the Apache License, Version 2.0 (the "License"); +    you may not use this file except in compliance with the License. +    You may obtain a copy of the License at + +        http://www.apache.org/licenses/LICENSE-2.0 + +    Unless required by applicable law or agreed to in writing, software +    distributed under the License is distributed on an "AS IS" BASIS, +    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +    See the License for the specific language governing permissions and +    limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F3xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0       Lowest...Highest. + * + * DMA priorities: + * 0...3        Lowest...Highest. + */ + +#define STM32F3xx_MCUCONF +#define STM32F303_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT                       FALSE +#define STM32_PVD_ENABLE                    FALSE +#define STM32_PLS                           STM32_PLS_LEV0 +#define STM32_HSI_ENABLED                   TRUE +#define STM32_LSI_ENABLED                   TRUE +#define STM32_HSE_ENABLED                   TRUE +#define STM32_LSE_ENABLED                   FALSE +#define STM32_SW                            STM32_SW_PLL +#define STM32_PLLSRC                        STM32_PLLSRC_HSE +#define STM32_PREDIV_VALUE                  1 +#define STM32_PLLMUL_VALUE                  9 +#define STM32_HPRE                          STM32_HPRE_DIV1 +#define STM32_PPRE1                         STM32_PPRE1_DIV2 +#define STM32_PPRE2                         STM32_PPRE2_DIV2 +#define STM32_MCOSEL                        STM32_MCOSEL_NOCLOCK +#define STM32_ADC12PRES                     STM32_ADC12PRES_DIV1 +#define STM32_ADC34PRES                     STM32_ADC34PRES_DIV1 +#define STM32_USART1SW                      STM32_USART1SW_PCLK +#define STM32_USART2SW                      STM32_USART2SW_PCLK +#define STM32_USART3SW                      STM32_USART3SW_PCLK +#define STM32_UART4SW                       STM32_UART4SW_PCLK +#define STM32_UART5SW                       STM32_UART5SW_PCLK +#define STM32_I2C1SW                        STM32_I2C1SW_SYSCLK +#define STM32_I2C2SW                        STM32_I2C2SW_SYSCLK +#define STM32_TIM1SW                        STM32_TIM1SW_PCLK2 +#define STM32_TIM8SW                        STM32_TIM8SW_PCLK2 +#define STM32_RTCSEL                        STM32_RTCSEL_LSI +#define STM32_USB_CLOCK_REQUIRED            TRUE +#define STM32_USBPRE                        STM32_USBPRE_DIV1P5 + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY            6 +#define STM32_IRQ_EXTI1_PRIORITY            6 +#define STM32_IRQ_EXTI2_PRIORITY            6 +#define STM32_IRQ_EXTI3_PRIORITY            6 +#define STM32_IRQ_EXTI4_PRIORITY            6 +#define STM32_IRQ_EXTI5_9_PRIORITY          6 +#define STM32_IRQ_EXTI10_15_PRIORITY        6 +#define STM32_IRQ_EXTI16_PRIORITY           6 +#define STM32_IRQ_EXTI17_PRIORITY           15 +#define STM32_IRQ_EXTI18_PRIORITY           6 +#define STM32_IRQ_EXTI19_PRIORITY           15 +#define STM32_IRQ_EXTI20_PRIORITY           15 +#define STM32_IRQ_EXTI21_22_29_PRIORITY     6 +#define STM32_IRQ_EXTI30_32_PRIORITY        6 +#define STM32_IRQ_EXTI33_PRIORITY           6 +#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY   7 +#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY    7 +#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7 +#define STM32_IRQ_TIM1_CC_PRIORITY          7 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_DUAL_MODE                 FALSE +#define STM32_ADC_COMPACT_SAMPLES           FALSE +#define STM32_ADC_USE_ADC1                  FALSE +#define STM32_ADC_USE_ADC2                  FALSE +#define STM32_ADC_USE_ADC3                  FALSE +#define STM32_ADC_USE_ADC4                  FALSE +#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(1, 1) +#define STM32_ADC_ADC2_DMA_STREAM           STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC3_DMA_STREAM           STM32_DMA_STREAM_ID(2, 5) +#define STM32_ADC_ADC4_DMA_STREAM           STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC1_DMA_PRIORITY         2 +#define STM32_ADC_ADC2_DMA_PRIORITY         2 +#define STM32_ADC_ADC3_DMA_PRIORITY         2 +#define STM32_ADC_ADC4_DMA_PRIORITY         2 +#define STM32_ADC_ADC12_IRQ_PRIORITY        5 +#define STM32_ADC_ADC3_IRQ_PRIORITY         5 +#define STM32_ADC_ADC4_IRQ_PRIORITY         5 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     5 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY     5 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY     5 +#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY     5 +#define STM32_ADC_ADC12_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC_ADC34_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1                  FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY         11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE                 FALSE +#define STM32_DAC_USE_DAC1_CH1              TRUE +#define STM32_DAC_USE_DAC1_CH2              TRUE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY     10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY     10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY     2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY     2 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1                  FALSE +#define STM32_GPT_USE_TIM2                  FALSE +#define STM32_GPT_USE_TIM3                  FALSE +#define STM32_GPT_USE_TIM4                  FALSE +#define STM32_GPT_USE_TIM6                  TRUE +#define STM32_GPT_USE_TIM7                  TRUE +#define STM32_GPT_USE_TIM8                  TRUE +#define STM32_GPT_USE_TIM15                 FALSE +#define STM32_GPT_USE_TIM16                 FALSE +#define STM32_GPT_USE_TIM17                 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY         7 +#define STM32_GPT_TIM2_IRQ_PRIORITY         7 +#define STM32_GPT_TIM3_IRQ_PRIORITY         7 +#define STM32_GPT_TIM4_IRQ_PRIORITY         7 +#define STM32_GPT_TIM6_IRQ_PRIORITY         7 +#define STM32_GPT_TIM7_IRQ_PRIORITY         7 +#define STM32_GPT_TIM8_IRQ_PRIORITY         7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1                  TRUE +#define STM32_I2C_USE_I2C2                  FALSE +#define STM32_I2C_BUSY_TIMEOUT              50 +#define STM32_I2C_I2C1_IRQ_PRIORITY         10 +#define STM32_I2C_I2C2_IRQ_PRIORITY         10 +#define STM32_I2C_USE_DMA                   TRUE +#define STM32_I2C_I2C1_DMA_PRIORITY         1 +#define STM32_I2C_I2C2_DMA_PRIORITY         1 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp)      osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1                  FALSE +#define STM32_ICU_USE_TIM2                  FALSE +#define STM32_ICU_USE_TIM3                  FALSE +#define STM32_ICU_USE_TIM4                  FALSE +#define STM32_ICU_USE_TIM8                  FALSE +#define STM32_ICU_USE_TIM15                 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY         7 +#define STM32_ICU_TIM2_IRQ_PRIORITY         7 +#define STM32_ICU_TIM3_IRQ_PRIORITY         7 +#define STM32_ICU_TIM4_IRQ_PRIORITY         7 +#define STM32_ICU_TIM8_IRQ_PRIORITY         7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED              FALSE +#define STM32_PWM_USE_TIM1                  FALSE +#define STM32_PWM_USE_TIM2                  FALSE +#define STM32_PWM_USE_TIM3                  TRUE +#define STM32_PWM_USE_TIM4                  TRUE +#define STM32_PWM_USE_TIM8                  FALSE +#define STM32_PWM_USE_TIM15                 FALSE +#define STM32_PWM_USE_TIM16                 FALSE +#define STM32_PWM_USE_TIM17                 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY         7 +#define STM32_PWM_TIM2_IRQ_PRIORITY         7 +#define STM32_PWM_TIM3_IRQ_PRIORITY         7 +#define STM32_PWM_TIM4_IRQ_PRIORITY         7 +#define STM32_PWM_TIM8_IRQ_PRIORITY         7 + +/* + * RTC driver system settings. + */ +#define STM32_RTC_PRESA_VALUE               32 +#define STM32_RTC_PRESS_VALUE               1024 +#define STM32_RTC_CR_INIT                   0 +#define STM32_RTC_TAMPCR_INIT               0 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1             FALSE +#define STM32_SERIAL_USE_USART2             TRUE +#define STM32_SERIAL_USE_USART3             FALSE +#define STM32_SERIAL_USE_UART4              FALSE +#define STM32_SERIAL_USE_UART5              FALSE +#define STM32_SERIAL_USART1_PRIORITY        12 +#define STM32_SERIAL_USART2_PRIORITY        12 +#define STM32_SERIAL_USART3_PRIORITY        12 +#define STM32_SERIAL_UART4_PRIORITY         12 +#define STM32_SERIAL_UART5_PRIORITY         12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1                  FALSE +#define STM32_SPI_USE_SPI2                  TRUE +#define STM32_SPI_USE_SPI3                  FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY         1 +#define STM32_SPI_SPI2_DMA_PRIORITY         1 +#define STM32_SPI_SPI3_DMA_PRIORITY         1 +#define STM32_SPI_SPI1_IRQ_PRIORITY         10 +#define STM32_SPI_SPI2_IRQ_PRIORITY         10 +#define STM32_SPI_SPI3_IRQ_PRIORITY         10 +#define STM32_SPI_DMA_ERROR_HOOK(spip)      osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY               8 +#define STM32_ST_USE_TIMER                  2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1               FALSE +#define STM32_UART_USE_USART2               FALSE +#define STM32_UART_USE_USART3               FALSE +#define STM32_UART_USART1_IRQ_PRIORITY      12 +#define STM32_UART_USART2_IRQ_PRIORITY      12 +#define STM32_UART_USART3_IRQ_PRIORITY      12 +#define STM32_UART_USART1_DMA_PRIORITY      0 +#define STM32_UART_USART2_DMA_PRIORITY      0 +#define STM32_UART_USART3_DMA_PRIORITY      0 +#define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1                  TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND      FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY      13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY      14 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG                  FALSE + +#endif /* MCUCONF_H */ diff --git a/platforms/chibios/GENERIC_STM32_F303XC/configs/proton_c.mk b/platforms/chibios/GENERIC_STM32_F303XC/configs/proton_c.mk new file mode 100644 index 0000000000..23907c810a --- /dev/null +++ b/platforms/chibios/GENERIC_STM32_F303XC/configs/proton_c.mk @@ -0,0 +1,9 @@ +# Proton C MCU settings for converting AVR projects +MCU = STM32F303 + +# These are defaults based on what has been implemented for ARM boards +AUDIO_ENABLE = yes +WS2812_DRIVER = bitbang + +# Force task driven PWM until ARM can provide automatic configuration +BACKLIGHT_DRIVER = software diff --git a/platforms/chibios/IC_TEENSY_3_1/board/board.c b/platforms/chibios/IC_TEENSY_3_1/board/board.c new file mode 100644 index 0000000000..63e3f64929 --- /dev/null +++ b/platforms/chibios/IC_TEENSY_3_1/board/board.c @@ -0,0 +1,146 @@ +/* +    ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde + +    Licensed under the Apache License, Version 2.0 (the "License"); +    you may not use this file except in compliance with the License. +    You may obtain a copy of the License at + +        http://www.apache.org/licenses/LICENSE-2.0 + +    Unless required by applicable law or agreed to in writing, software +    distributed under the License is distributed on an "AS IS" BASIS, +    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +    See the License for the specific language governing permissions and +    limitations under the License. +*/ +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/** + * @brief   PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + *          This variable is used by the HAL when initializing the PAL driver. + */ +const PALConfig pal_default_config = { +    .ports = +        { +            { +                /* +                 * PORTA setup. +                 * +                 * PTA4  - PIN33 +                 * PTA5  - PIN24 +                 * PTA12 - PIN3 +                 * PTA13 - PIN4 +                 * +                 * PTA18/19 crystal +                 * PTA0/3 SWD +                 */ +                .port = IOPORT1, +                .pads = +                    { +                        PAL_MODE_ALTERNATIVE_7, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_ALTERNATIVE_7, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_INPUT_ANALOG, PAL_MODE_INPUT_ANALOG, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, +                    }, +            }, +            { +                /* +                 * PORTB setup. +                 * +                 * PTB0  - PIN16 +                 * PTB1  - PIN17 +                 * PTB2  - PIN19 +                 * PTB3  - PIN18 +                 * PTB16 - PIN0 - UART0_TX +                 * PTB17 - PIN1 - UART0_RX +                 * PTB18 - PIN32 +                 * PTB19 - PIN25 +                 */ +                .port = IOPORT2, +                .pads = +                    { +                        PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_ALTERNATIVE_3, PAL_MODE_ALTERNATIVE_3, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, +                    }, +            }, +            { +                /* +                 * PORTC setup. +                 * +                 * PTC0  - PIN15 +                 * PTC1  - PIN22 +                 * PTC2  - PIN23 +                 * PTC3  - PIN9 +                 * PTC4  - PIN10 +                 * PTC5  - PIN13 +                 * PTC6  - PIN11 +                 * PTC7  - PIN12 +                 * PTC8  - PIN28 +                 * PTC9  - PIN27 +                 * PTC10 - PIN29 +                 * PTC11 - PIN30 +                 */ +                .port = IOPORT3, +                .pads = +                    { +                        PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, +                    }, +            }, +            { +                /* +                 * PORTD setup. +                 * +                 * PTD0  - PIN2 +                 * PTD1  - PIN14 +                 * PTD2  - PIN7 +                 * PTD3  - PIN8 +                 * PTD4  - PIN6 +                 * PTD5  - PIN20 +                 * PTD6  - PIN21 +                 * PTD7  - PIN5 +                 */ +                .port = IOPORT4, +                .pads = +                    { +                        PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, +                    }, +            }, +            { +                /* +                 * PORTE setup. +                 * +                 * PTE0  - PIN31 +                 * PTE1  - PIN26 +                 */ +                .port = IOPORT5, +                .pads = +                    { +                        PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, +                    }, +            }, +        }, +}; +#endif + +// NOTE: This value comes from kiibohd/controller and is the location of a value +// which needs to be checked before disabling the watchdog (which happens in +// k20x_clock_init) +#define WDOG_TMROUTL *(volatile uint16_t *)0x40052012 + +/** + * @brief   Early initialization code. + * @details This initialization must be performed just after stack setup + *          and before any other initialization. + */ +void __early_init(void) { +    // This is a dirty hack and should only be used as a temporary fix until this +    // is upstreamed. +    while (WDOG_TMROUTL < 2) +        ;  // Must wait for WDOG timer if already running, before jumping + +    k20x_clock_init(); +} + +/** + * @brief   Board-specific initialization code. + * @todo    Add your board-specific code, if any. + */ +void boardInit(void) {} diff --git a/platforms/chibios/IC_TEENSY_3_1/board/board.h b/platforms/chibios/IC_TEENSY_3_1/board/board.h new file mode 100644 index 0000000000..c8259ab0c7 --- /dev/null +++ b/platforms/chibios/IC_TEENSY_3_1/board/board.h @@ -0,0 +1,295 @@ +/* +    ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde + +    Licensed under the Apache License, Version 2.0 (the "License"); +    you may not use this file except in compliance with the License. +    You may obtain a copy of the License at + +        http://www.apache.org/licenses/LICENSE-2.0 + +    Unless required by applicable law or agreed to in writing, software +    distributed under the License is distributed on an "AS IS" BASIS, +    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +    See the License for the specific language governing permissions and +    limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for the PJRC Teensy 3.1 board. + */ + +/* + * Board identifier. + */ +#define BOARD_PJRC_TEENSY_3_1 +#define BOARD_NAME "PJRC Teensy 3.1" + +/* External 16 MHz crystal */ +#define KINETIS_XTAL_FREQUENCY 16000000UL + +/* Use internal capacitors for the crystal */ +#define KINETIS_BOARD_OSCILLATOR_SETTING OSC_CR_SC8P | OSC_CR_SC2P + +/* + * MCU type + */ +#define K20x7 + +/* + * IO pins assignments. + */ +#define PORTA_PIN0 0 +#define PORTA_PIN1 1 +#define PORTA_PIN2 2 +#define PORTA_PIN3 3 +#define TEENSY_PIN33 4 +#define TEENSY_PIN24 5 +#define PORTA_PIN6 6 +#define PORTA_PIN7 7 +#define PORTA_PIN8 8 +#define PORTA_PIN9 9 +#define PORTA_PIN10 10 +#define PORTA_PIN11 11 +#define TEENSY_PIN3 12 +#define TEENSY_PIN4 13 +#define PORTA_PIN14 14 +#define PORTA_PIN15 15 +#define PORTA_PIN16 16 +#define PORTA_PIN17 17 +#define PORTA_PIN18 18 +#define PORTA_PIN19 19 +#define PORTA_PIN20 20 +#define PORTA_PIN21 21 +#define PORTA_PIN22 22 +#define PORTA_PIN23 23 +#define PORTA_PIN24 24 +#define PORTA_PIN25 25 +#define PORTA_PIN26 26 +#define PORTA_PIN27 27 +#define PORTA_PIN28 28 +#define PORTA_PIN29 29 +#define PORTA_PIN30 30 +#define PORTA_PIN31 31 + +#define TEENSY_PIN3_IOPORT IOPORT1 +#define TEENSY_PIN4_IOPORT IOPORT1 +#define TEENSY_PIN24_IOPORT IOPORT1 +#define TEENSY_PIN33_IOPORT IOPORT1 + +#define TEENSY_PIN16 0 +#define TEENSY_PIN17 1 +#define TEENSY_PIN19 2 +#define TEENSY_PIN18 3 +#define PORTB_PIN4 4 +#define PORTB_PIN5 5 +#define PORTB_PIN6 6 +#define PORTB_PIN7 7 +#define PORTB_PIN8 8 +#define PORTB_PIN9 9 +#define PORTB_PIN10 10 +#define PORTB_PIN11 11 +#define PORTB_PIN12 12 +#define PORTB_PIN13 13 +#define PORTB_PIN14 14 +#define PORTB_PIN15 15 +#define TEENSY_PIN0 16 +#define TEENSY_PIN1 17 +#define TEENSY_PIN32 18 +#define TEENSY_PIN25 19 +#define PORTB_PIN20 20 +#define PORTB_PIN21 21 +#define PORTB_PIN22 22 +#define PORTB_PIN23 23 +#define PORTB_PIN24 24 +#define PORTB_PIN25 25 +#define PORTB_PIN26 26 +#define PORTB_PIN27 27 +#define PORTB_PIN28 28 +#define PORTB_PIN29 29 +#define PORTB_PIN30 30 +#define PORTB_PIN31 31 + +#define TEENSY_PIN0_IOPORT IOPORT2 +#define TEENSY_PIN1_IOPORT IOPORT2 +#define TEENSY_PIN16_IOPORT IOPORT2 +#define TEENSY_PIN17_IOPORT IOPORT2 +#define TEENSY_PIN18_IOPORT IOPORT2 +#define TEENSY_PIN19_IOPORT IOPORT2 +#define TEENSY_PIN25_IOPORT IOPORT2 +#define TEENSY_PIN32_IOPORT IOPORT2 + +#define TEENSY_PIN15 0 +#define TEENSY_PIN22 1 +#define TEENSY_PIN23 2 +#define TEENSY_PIN9 3 +#define TEENSY_PIN10 4 +#define TEENSY_PIN13 5 +#define TEENSY_PIN11 6 +#define TEENSY_PIN12 7 +#define TEENSY_PIN28 8 +#define TEENSY_PIN27 9 +#define TEENSY_PIN29 10 +#define TEENSY_PIN30 11 +#define PORTC_PIN12 12 +#define PORTC_PIN13 13 +#define PORTC_PIN14 14 +#define PORTC_PIN15 15 +#define PORTC_PIN16 16 +#define PORTC_PIN17 17 +#define PORTC_PIN18 18 +#define PORTC_PIN19 19 +#define PORTC_PIN20 20 +#define PORTC_PIN21 21 +#define PORTC_PIN22 22 +#define PORTC_PIN23 23 +#define PORTC_PIN24 24 +#define PORTC_PIN25 25 +#define PORTC_PIN26 26 +#define PORTC_PIN27 27 +#define PORTC_PIN28 28 +#define PORTC_PIN29 29 +#define PORTC_PIN30 30 +#define PORTC_PIN31 31 + +#define TEENSY_PIN9_IOPORT IOPORT3 +#define TEENSY_PIN10_IOPORT IOPORT3 +#define TEENSY_PIN11_IOPORT IOPORT3 +#define TEENSY_PIN12_IOPORT IOPORT3 +#define TEENSY_PIN13_IOPORT IOPORT3 +#define TEENSY_PIN15_IOPORT IOPORT3 +#define TEENSY_PIN22_IOPORT IOPORT3 +#define TEENSY_PIN23_IOPORT IOPORT3 +#define TEENSY_PIN27_IOPORT IOPORT3 +#define TEENSY_PIN28_IOPORT IOPORT3 +#define TEENSY_PIN29_IOPORT IOPORT3 +#define TEENSY_PIN30_IOPORT IOPORT3 + +#define TEENSY_PIN2 0 +#define TEENSY_PIN14 1 +#define TEENSY_PIN7 2 +#define TEENSY_PIN8 3 +#define TEENSY_PIN6 4 +#define TEENSY_PIN20 5 +#define TEENSY_PIN21 6 +#define TEENSY_PIN5 7 +#define PORTD_PIN8 8 +#define PORTD_PIN9 9 +#define PORTD_PIN10 10 +#define PORTD_PIN11 11 +#define PORTD_PIN12 12 +#define PORTD_PIN13 13 +#define PORTD_PIN14 14 +#define PORTD_PIN15 15 +#define PORTD_PIN16 16 +#define PORTD_PIN17 17 +#define PORTD_PIN18 18 +#define PORTD_PIN19 19 +#define PORTD_PIN20 20 +#define PORTD_PIN21 21 +#define PORTD_PIN22 22 +#define PORTD_PIN23 23 +#define PORTD_PIN24 24 +#define PORTD_PIN25 25 +#define PORTD_PIN26 26 +#define PORTD_PIN27 27 +#define PORTD_PIN28 28 +#define PORTD_PIN29 29 +#define PORTD_PIN30 30 +#define PORTD_PIN31 31 + +#define TEENSY_PIN2_IOPORT IOPORT4 +#define TEENSY_PIN5_IOPORT IOPORT4 +#define TEENSY_PIN6_IOPORT IOPORT4 +#define TEENSY_PIN7_IOPORT IOPORT4 +#define TEENSY_PIN8_IOPORT IOPORT4 +#define TEENSY_PIN14_IOPORT IOPORT4 +#define TEENSY_PIN20_IOPORT IOPORT4 +#define TEENSY_PIN21_IOPORT IOPORT4 + +#define TEENSY_PIN31 0 +#define TEENSY_PIN26 1 +#define PORTE_PIN2 2 +#define PORTE_PIN3 3 +#define PORTE_PIN4 4 +#define PORTE_PIN5 5 +#define PORTE_PIN6 6 +#define PORTE_PIN7 7 +#define PORTE_PIN8 8 +#define PORTE_PIN9 9 +#define PORTE_PIN10 10 +#define PORTE_PIN11 11 +#define PORTE_PIN12 12 +#define PORTE_PIN13 13 +#define PORTE_PIN14 14 +#define PORTE_PIN15 15 +#define PORTE_PIN16 16 +#define PORTE_PIN17 17 +#define PORTE_PIN18 18 +#define PORTE_PIN19 19 +#define PORTE_PIN20 20 +#define PORTE_PIN21 21 +#define PORTE_PIN22 22 +#define PORTE_PIN23 23 +#define PORTE_PIN24 24 +#define PORTE_PIN25 25 +#define PORTE_PIN26 26 +#define PORTE_PIN27 27 +#define PORTE_PIN28 28 +#define PORTE_PIN29 29 +#define PORTE_PIN30 30 +#define PORTE_PIN31 31 + +#define TEENSY_PIN26_IOPORT IOPORT5 +#define TEENSY_PIN31_IOPORT IOPORT5 + +#define LINE_PIN1 PAL_LINE(TEENSY_PIN1_IOPORT, TEENSY_PIN1) +#define LINE_PIN2 PAL_LINE(TEENSY_PIN2_IOPORT, TEENSY_PIN2) +#define LINE_PIN3 PAL_LINE(TEENSY_PIN3_IOPORT, TEENSY_PIN3) +#define LINE_PIN4 PAL_LINE(TEENSY_PIN4_IOPORT, TEENSY_PIN4) +#define LINE_PIN5 PAL_LINE(TEENSY_PIN5_IOPORT, TEENSY_PIN5) +#define LINE_PIN6 PAL_LINE(TEENSY_PIN6_IOPORT, TEENSY_PIN6) +#define LINE_PIN7 PAL_LINE(TEENSY_PIN7_IOPORT, TEENSY_PIN7) +#define LINE_PIN8 PAL_LINE(TEENSY_PIN8_IOPORT, TEENSY_PIN8) +#define LINE_PIN9 PAL_LINE(TEENSY_PIN9_IOPORT, TEENSY_PIN9) +#define LINE_PIN10 PAL_LINE(TEENSY_PIN10_IOPORT, TEENSY_PIN10) +#define LINE_PIN11 PAL_LINE(TEENSY_PIN11_IOPORT, TEENSY_PIN11) +#define LINE_PIN12 PAL_LINE(TEENSY_PIN12_IOPORT, TEENSY_PIN12) +#define LINE_PIN13 PAL_LINE(TEENSY_PIN13_IOPORT, TEENSY_PIN13) +#define LINE_PIN14 PAL_LINE(TEENSY_PIN14_IOPORT, TEENSY_PIN14) +#define LINE_PIN15 PAL_LINE(TEENSY_PIN15_IOPORT, TEENSY_PIN15) +#define LINE_PIN16 PAL_LINE(TEENSY_PIN16_IOPORT, TEENSY_PIN16) +#define LINE_PIN17 PAL_LINE(TEENSY_PIN17_IOPORT, TEENSY_PIN17) +#define LINE_PIN18 PAL_LINE(TEENSY_PIN18_IOPORT, TEENSY_PIN18) +#define LINE_PIN19 PAL_LINE(TEENSY_PIN19_IOPORT, TEENSY_PIN19) +#define LINE_PIN20 PAL_LINE(TEENSY_PIN20_IOPORT, TEENSY_PIN20) +#define LINE_PIN21 PAL_LINE(TEENSY_PIN21_IOPORT, TEENSY_PIN21) +#define LINE_PIN22 PAL_LINE(TEENSY_PIN22_IOPORT, TEENSY_PIN22) +#define LINE_PIN23 PAL_LINE(TEENSY_PIN23_IOPORT, TEENSY_PIN23) +#define LINE_PIN24 PAL_LINE(TEENSY_PIN24_IOPORT, TEENSY_PIN24) +#define LINE_PIN25 PAL_LINE(TEENSY_PIN25_IOPORT, TEENSY_PIN25) +#define LINE_PIN25 PAL_LINE(TEENSY_PIN25_IOPORT, TEENSY_PIN25) +#define LINE_PIN26 PAL_LINE(TEENSY_PIN26_IOPORT, TEENSY_PIN26) +#define LINE_PIN27 PAL_LINE(TEENSY_PIN27_IOPORT, TEENSY_PIN27) +#define LINE_PIN28 PAL_LINE(TEENSY_PIN28_IOPORT, TEENSY_PIN28) +#define LINE_PIN29 PAL_LINE(TEENSY_PIN29_IOPORT, TEENSY_PIN29) +#define LINE_PIN30 PAL_LINE(TEENSY_PIN30_IOPORT, TEENSY_PIN30) +#define LINE_PIN31 PAL_LINE(TEENSY_PIN31_IOPORT, TEENSY_PIN31) +#define LINE_PIN32 PAL_LINE(TEENSY_PIN32_IOPORT, TEENSY_PIN32) +#define LINE_PIN33 PAL_LINE(TEENSY_PIN33_IOPORT, TEENSY_PIN33) + +#define LINE_LED LINE_PIN13 + +#if !defined(_FROM_ASM_) +#    ifdef __cplusplus +extern "C" { +#    endif +void boardInit(void); +#    ifdef __cplusplus +} +#    endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/platforms/chibios/IC_TEENSY_3_1/board/board.mk b/platforms/chibios/IC_TEENSY_3_1/board/board.mk new file mode 100644 index 0000000000..842e335905 --- /dev/null +++ b/platforms/chibios/IC_TEENSY_3_1/board/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = $(BOARD_PATH)/board/board.c + +# Required include directories +BOARDINC = $(BOARD_PATH)/board + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC  += $(BOARDINC) diff --git a/platforms/chibios/STM32_F103_STM32DUINO/board/board.c b/platforms/chibios/STM32_F103_STM32DUINO/board/board.c new file mode 100644 index 0000000000..9135f61364 --- /dev/null +++ b/platforms/chibios/STM32_F103_STM32DUINO/board/board.c @@ -0,0 +1,59 @@ +/* +    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + +    Licensed under the Apache License, Version 2.0 (the "License"); +    you may not use this file except in compliance with the License. +    You may obtain a copy of the License at + +        http://www.apache.org/licenses/LICENSE-2.0 + +    Unless required by applicable law or agreed to in writing, software +    distributed under the License is distributed on an "AS IS" BASIS, +    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +    See the License for the specific language governing permissions and +    limitations under the License. +*/ + +#include "hal.h" + +// Value to place in RTC backup register 10 for persistent bootloader mode +#define RTC_BOOTLOADER_FLAG 0x424C + +/** + * @brief   PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + *          This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = +{ +  {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH}, +  {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH}, +  {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH}, +  {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH}, +  {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH}, +}; +#endif + +__attribute__((weak)) void enter_bootloader_mode_if_requested(void) {} + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { +  enter_bootloader_mode_if_requested(); + +  stm32_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) { +   //JTAG-DP Disabled and SW-DP Enabled +   AFIO->MAPR |= AFIO_MAPR_SWJ_CFG_JTAGDISABLE; +   //Set backup register DR10 to enter bootloader on reset +   BKP->DR10 = RTC_BOOTLOADER_FLAG; +} diff --git a/platforms/chibios/STM32_F103_STM32DUINO/board/board.h b/platforms/chibios/STM32_F103_STM32DUINO/board/board.h new file mode 100644 index 0000000000..09d182d6ca --- /dev/null +++ b/platforms/chibios/STM32_F103_STM32DUINO/board/board.h @@ -0,0 +1,166 @@ +/* +    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + +    Licensed under the Apache License, Version 2.0 (the "License"); +    you may not use this file except in compliance with the License. +    You may obtain a copy of the License at + +        http://www.apache.org/licenses/LICENSE-2.0 + +    Unless required by applicable law or agreed to in writing, software +    distributed under the License is distributed on an "AS IS" BASIS, +    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +    See the License for the specific language governing permissions and +    limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for a Generic STM32F103 board. + */ + +/* + * Board identifier. + */ +#define BOARD_STM32_F103_STM32DUINO +#define BOARD_NAME              "GENERIC STM32F103C8T6 board - stm32duino bootloader" + +/* + * Board frequencies. + */ +#define STM32_LSECLK            32768 +#define STM32_HSECLK            8000000 + +/* + * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h. + */ +#define STM32F103xB + +/* + * IO pins assignments + */ + +/* on-board */ + +#define GPIOA_LED               8 +#define GPIOD_OSC_IN            0 +#define GPIOD_OSC_OUT           1 + +/* In case your board has a "USB enable" hardware +   controlled by a pin, define it here. (It could be just +   a 1.5k resistor connected to D+ line.) +*/ +/* +#define GPIOB_USB_DISC          10 +*/ + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * + * The digits have the following meaning: + *   0 - Analog input. + *   1 - Push Pull output 10MHz. + *   2 - Push Pull output 2MHz. + *   3 - Push Pull output 50MHz. + *   4 - Digital input. + *   5 - Open Drain output 10MHz. + *   6 - Open Drain output 2MHz. + *   7 - Open Drain output 50MHz. + *   8 - Digital input with PullUp or PullDown resistor depending on ODR. + *   9 - Alternate Push Pull output 10MHz. + *   A - Alternate Push Pull output 2MHz. + *   B - Alternate Push Pull output 50MHz. + *   C - Reserved. + *   D - Alternate Open Drain output 10MHz. + *   E - Alternate Open Drain output 2MHz. + *   F - Alternate Open Drain output 50MHz. + * Please refer to the STM32 Reference Manual for details. + */ + +/* + * Port A setup. + * Everything input with pull-up except: + * PA2  - Alternate output  (USART2 TX). + * PA3  - Normal input      (USART2 RX). + * PA9  - Alternate output  (USART1 TX). + * PA10 - Normal input      (USART1 RX). + */ +#define VAL_GPIOACRL            0x88884B88      /*  PA7...PA0 */ +#define VAL_GPIOACRH            0x888884B8      /* PA15...PA8 */ +#define VAL_GPIOAODR            0xFFFFFFFF + +/* + * Port B setup. + * Everything input with pull-up except: + * PB10    - Push Pull output  (USB switch). + */ +#define VAL_GPIOBCRL            0x88888888      /*  PB7...PB0 */ +#define VAL_GPIOBCRH            0x88888388      /* PB15...PB8 */ +#define VAL_GPIOBODR            0xFFFFFFFF + +/* + * Port C setup. + * Everything input with pull-up except: + * PC13    - Push Pull output  (LED). + */ +#define VAL_GPIOCCRL            0x88888888      /*  PC7...PC0 */ +#define VAL_GPIOCCRH            0x88388888      /* PC15...PC8 */ +#define VAL_GPIOCODR            0xFFFFFFFF + +/* + * Port D setup. + * Everything input with pull-up except: + * PD0  - Normal input (XTAL). + * PD1  - Normal input (XTAL). + */ +#define VAL_GPIODCRL            0x88888844      /*  PD7...PD0 */ +#define VAL_GPIODCRH            0x88888888      /* PD15...PD8 */ +#define VAL_GPIODODR            0xFFFFFFFF + +/* + * Port E setup. + * Everything input with pull-up except: + */ +#define VAL_GPIOECRL            0x88888888      /*  PE7...PE0 */ +#define VAL_GPIOECRH            0x88888888      /* PE15...PE8 */ +#define VAL_GPIOEODR            0xFFFFFFFF + +/* + * USB bus activation macro, required by the USB driver. + */ +/* The point is that most of the generic STM32F103* boards +   have a 1.5k resistor connected on one end to the D+ line +   and on the other end to some pin. Or even a slightly more +   complicated "USB enable" circuit, controlled by a pin. +   That should go here. + +   However on some boards (e.g. one that I have), there's no +   such hardware. In which case it's better to not do anything. +*/ +/* +#define usb_lld_connect_bus(usbp) palClearPad(GPIOB, GPIOB_USB_DISC) +*/ +#define usb_lld_connect_bus(usbp) palSetPadMode(GPIOA, 12, PAL_MODE_INPUT); + +/* + * USB bus de-activation macro, required by the USB driver. + */ +/* +#define usb_lld_disconnect_bus(usbp) palSetPad(GPIOB, GPIOB_USB_DISC) +*/ +#define usb_lld_disconnect_bus(usbp) palSetPadMode(GPIOA, 12, PAL_MODE_OUTPUT_PUSHPULL); palClearPad(GPIOA, 12); + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif +  void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/platforms/chibios/STM32_F103_STM32DUINO/board/board.mk b/platforms/chibios/STM32_F103_STM32DUINO/board/board.mk new file mode 100644 index 0000000000..842e335905 --- /dev/null +++ b/platforms/chibios/STM32_F103_STM32DUINO/board/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = $(BOARD_PATH)/board/board.c + +# Required include directories +BOARDINC = $(BOARD_PATH)/board + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC  += $(BOARDINC) diff --git a/platforms/chibios/keyboard-config-templates/board.h b/platforms/chibios/keyboard-config-templates/board.h new file mode 100644 index 0000000000..967ec13a1c --- /dev/null +++ b/platforms/chibios/keyboard-config-templates/board.h @@ -0,0 +1,20 @@ +/* Copyright 2020 Nick Brassel (tzarc) + * + *  This program is free software: you can redistribute it and/or modify + *  it under the terms of the GNU General Public License as published by + *  the Free Software Foundation, either version 3 of the License, or + *  (at your option) any later version. + * + *  This program is distributed in the hope that it will be useful, + *  but WITHOUT ANY WARRANTY; without even the implied warranty of + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the + *  GNU General Public License for more details. + * + *  You should have received a copy of the GNU General Public License + *  along with this program.  If not, see <https://www.gnu.org/licenses/>. + */ +#pragma once + +#include_next "board.h" + +// #undef STM32_HSE_BYPASS diff --git a/platforms/chibios/keyboard-config-templates/chconf.h b/platforms/chibios/keyboard-config-templates/chconf.h new file mode 100644 index 0000000000..7c2af93f5e --- /dev/null +++ b/platforms/chibios/keyboard-config-templates/chconf.h @@ -0,0 +1,20 @@ +/* Copyright 2020 Nick Brassel (tzarc) + * + *  This program is free software: you can redistribute it and/or modify + *  it under the terms of the GNU General Public License as published by + *  the Free Software Foundation, either version 3 of the License, or + *  (at your option) any later version. + * + *  This program is distributed in the hope that it will be useful, + *  but WITHOUT ANY WARRANTY; without even the implied warranty of + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the + *  GNU General Public License for more details. + * + *  You should have received a copy of the GNU General Public License + *  along with this program.  If not, see <https://www.gnu.org/licenses/>. + */ +#pragma once + +// #define CH_CFG_OPTIMIZE_SPEED TRUE + +#include_next "chconf.h" diff --git a/platforms/chibios/keyboard-config-templates/halconf.h b/platforms/chibios/keyboard-config-templates/halconf.h new file mode 100644 index 0000000000..ab5f738f97 --- /dev/null +++ b/platforms/chibios/keyboard-config-templates/halconf.h @@ -0,0 +1,20 @@ +/* Copyright 2020 Nick Brassel (tzarc) + * + *  This program is free software: you can redistribute it and/or modify + *  it under the terms of the GNU General Public License as published by + *  the Free Software Foundation, either version 3 of the License, or + *  (at your option) any later version. + * + *  This program is distributed in the hope that it will be useful, + *  but WITHOUT ANY WARRANTY; without even the implied warranty of + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the + *  GNU General Public License for more details. + * + *  You should have received a copy of the GNU General Public License + *  along with this program.  If not, see <https://www.gnu.org/licenses/>. + */ +#pragma once + +// #define HAL_USE_DAC TRUE + +#include_next "halconf.h" diff --git a/platforms/chibios/keyboard-config-templates/mcuconf.h b/platforms/chibios/keyboard-config-templates/mcuconf.h new file mode 100644 index 0000000000..5b42747b95 --- /dev/null +++ b/platforms/chibios/keyboard-config-templates/mcuconf.h @@ -0,0 +1,21 @@ +/* Copyright 2020 Nick Brassel (tzarc) + * + *  This program is free software: you can redistribute it and/or modify + *  it under the terms of the GNU General Public License as published by + *  the Free Software Foundation, either version 3 of the License, or + *  (at your option) any later version. + * + *  This program is distributed in the hope that it will be useful, + *  but WITHOUT ANY WARRANTY; without even the implied warranty of + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the + *  GNU General Public License for more details. + * + *  You should have received a copy of the GNU General Public License + *  along with this program.  If not, see <https://www.gnu.org/licenses/>. + */ +#pragma once + +#include_next "mcuconf.h" + +// #undef STM32_HSE_ENABLED +// #define STM32_HSE_ENABLED FALSE diff --git a/platforms/chibios/ld/MKL26Z64.ld b/platforms/chibios/ld/MKL26Z64.ld new file mode 100644 index 0000000000..c4ca8b874c --- /dev/null +++ b/platforms/chibios/ld/MKL26Z64.ld @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2013-2016 Fabio Utzig, http://fabioutzig.com + *           (C) 2016 flabbergast <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * KL26Z64 memory setup. + */ +MEMORY +{ +  flash0   : org = 0x00000000, len = 0x100 +  flash1   : org = 0x00000400, len = 0x10 +  flash2   : org = 0x00000410, len = 62k - 0x410 +  flash3   : org = 0x0000F800, len = 2k +  flash4   : org = 0x00000000, len = 0 +  flash5   : org = 0x00000000, len = 0 +  flash6   : org = 0x00000000, len = 0 +  flash7   : org = 0x00000000, len = 0 +  ram0     : org = 0x1FFFF800, len = 8k +  ram1     : org = 0x00000000, len = 0 +  ram2     : org = 0x00000000, len = 0 +  ram3     : org = 0x00000000, len = 0 +  ram4     : org = 0x00000000, len = 0 +  ram5     : org = 0x00000000, len = 0 +  ram6     : org = 0x00000000, len = 0 +  ram7     : org = 0x00000000, len = 0 +} + +/* Flash region for the configuration bytes.*/ +SECTIONS +{ +  .cfmprotect : ALIGN(4) SUBALIGN(4) +  { +    KEEP(*(.cfmconfig)) +  } > flash1 +} + +/* For each data/text section two region are defined, a virtual region +   and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash2); +REGION_ALIAS("XTORS_FLASH_LMA", flash2); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash2); +REGION_ALIAS("TEXT_FLASH_LMA", flash2); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash2); +REGION_ALIAS("RODATA_FLASH_LMA", flash2); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash2); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash2); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash2); + +/* RAM region to be used for Main stack. This stack accommodates the processing +   of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by +   the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash2); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +__eeprom_workarea_start__ = ORIGIN(flash3); +__eeprom_workarea_size__  = LENGTH(flash3); +__eeprom_workarea_end__   = __eeprom_workarea_start__ + __eeprom_workarea_size__; + +/* Generic rules inclusion.*/ +INCLUDE rules.ld diff --git a/platforms/chibios/ld/STM32F103x8_stm32duino_bootloader.ld b/platforms/chibios/ld/STM32F103x8_stm32duino_bootloader.ld new file mode 100644 index 0000000000..d0688ef601 --- /dev/null +++ b/platforms/chibios/ld/STM32F103x8_stm32duino_bootloader.ld @@ -0,0 +1,88 @@ +/* +    ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + +    Licensed under the Apache License, Version 2.0 (the "License"); +    you may not use this file except in compliance with the License. +    You may obtain a copy of the License at + +        http://www.apache.org/licenses/LICENSE-2.0 + +    Unless required by applicable law or agreed to in writing, software +    distributed under the License is distributed on an "AS IS" BASIS, +    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +    See the License for the specific language governing permissions and +    limitations under the License. +*/ + +/* + * ST32F103xB memory setup for use with the maplemini bootloader. + * You will have to + * 	#define CORTEX_VTOR_INIT 0x5000 + * in your projects chconf.h + */ +MEMORY +{ +    flash0  : org = 0x08002000, len = 64k - 0x2000 +    flash1  : org = 0x00000000, len = 0 +    flash2  : org = 0x00000000, len = 0 +    flash3  : org = 0x00000000, len = 0 +    flash4  : org = 0x00000000, len = 0 +    flash5  : org = 0x00000000, len = 0 +    flash6  : org = 0x00000000, len = 0 +    flash7  : org = 0x00000000, len = 0 +    ram0    : org = 0x20000000, len = 20k +    ram1    : org = 0x00000000, len = 0 +    ram2    : org = 0x00000000, len = 0 +    ram3    : org = 0x00000000, len = 0 +    ram4    : org = 0x00000000, len = 0 +    ram5    : org = 0x00000000, len = 0 +    ram6    : org = 0x00000000, len = 0 +    ram7    : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region +   and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing +   of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by +   the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Generic rules inclusion.*/ +INCLUDE rules.ld | 
