chipdev

commit 5b971562baea51a4683195d482f0141717f93738
parent a53ee0ac6053c053a7d61244cc20be4f87f4e5cf
Author: Jack Sangdahl <jack@pngu.org>
Date:   Wed, 19 Nov 2025 11:54:52 -0700

Add problem template

Diffstat:
A
template/Makefile
 | 
8
++++++++
A
template/foo.v
 | 
2
++
A
template/foo_test.py
 | 
6
++++++
A
template/readme.md
 | 
5
+++++

4 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/template/Makefile b/template/Makefile
@@ -0,0 +1,8 @@
+SIM = verilator
+TOPLEVEL_LANG = verilog
+VERILOG_SOURCES = $(PWD)/foo.v
+COCOTB_TOPLEVEL = model
+COCOTB_TEST_MODULES = foo_test
+WAVES = 1
+
+include $(shell cocotb-config --makefiles)/Makefile.sim
diff --git a/template/foo.v b/template/foo.v
@@ -0,0 +1,2 @@
+module model #() ();
+endmodule
diff --git a/template/foo_test.py b/template/foo_test.py
@@ -0,0 +1,6 @@
+import cocotb
+
+
+@cocotb.test()
+async def test_foo(dut):
+    """Testbench Code"""
diff --git a/template/readme.md b/template/readme.md
@@ -0,0 +1,5 @@
+# Foo
+
+## Prompt
+## Input & Output Signals
+## Example: