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author | Dean Camera <[email protected]> | 2010-06-24 08:12:27 +0000 |
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committer | Dean Camera <[email protected]> | 2010-06-24 08:12:27 +0000 |
commit | 55d7e1e65bccd6b4c44802cf971f39eb05e6e57a (patch) | |
tree | d85b5bb45497706d728d585bb404d9f7f936b226 | |
parent | ad29e79b944bbca136290c47869dfc30af676e7f (diff) | |
download | qmk_firmware-55d7e1e65bccd6b4c44802cf971f39eb05e6e57a.tar.gz qmk_firmware-55d7e1e65bccd6b4c44802cf971f39eb05e6e57a.zip |
Make XPLAINBridge serial bridge much more reliable for the reception of characters from the XMEGA through the software UART interface.
-rw-r--r-- | Projects/XPLAINBridge/Lib/SoftUART.c | 16 |
1 files changed, 5 insertions, 11 deletions
diff --git a/Projects/XPLAINBridge/Lib/SoftUART.c b/Projects/XPLAINBridge/Lib/SoftUART.c index a23ea456da..02223af982 100644 --- a/Projects/XPLAINBridge/Lib/SoftUART.c +++ b/Projects/XPLAINBridge/Lib/SoftUART.c @@ -79,18 +79,12 @@ ISR(INT0_vect, ISR_BLOCK) RX_Data = 0; RX_BitMask = (1 << 0); - /* Check that the start bit is still low to prevent noise from triggering a reception */ - if (!(SRXPIN & (1 << SRX))) - { - /* Clear reception channel ISR flag in case it is pending */ - TIFR1 = (1 << OCF1A); - - /* Still low, enable bit receive ISR */ - TIMSK1 = (1 << OCIE1A); + /* Clear reception channel ISR flag and enable the bit reception ISR */ + TIFR1 = (1 << OCF1A); + TIMSK1 = (1 << OCIE1A); - /* Clear the start bit detection ISR flag */ - EIMSK &= ~(1 << INT0); - } + /* Disable start bit detection ISR while the next byte is received */ + EIMSK &= ~(1 << INT0); } /** ISR to manage the reception of bits to the software UART. */ |