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-rw-r--r--platforms/chibios/drivers/analog.c23
-rw-r--r--platforms/chibios/drivers/backlight_pwm.c4
-rw-r--r--platforms/chibios/drivers/eeprom/eeprom_stm32_L0_L1.c45
-rw-r--r--platforms/chibios/drivers/i2c_master.c2
-rw-r--r--platforms/chibios/drivers/usbpd_stm32g4.c2
-rw-r--r--platforms/chibios/drivers/wear_leveling/wear_leveling_efl.c1
-rw-r--r--platforms/chibios/drivers/wear_leveling/wear_leveling_legacy.c1
-rw-r--r--platforms/chibios/drivers/wear_leveling/wear_leveling_rp2040_flash.c7
8 files changed, 68 insertions, 17 deletions
diff --git a/platforms/chibios/drivers/analog.c b/platforms/chibios/drivers/analog.c
index 7e1f87e6c9..a916cc9a1d 100644
--- a/platforms/chibios/drivers/analog.c
+++ b/platforms/chibios/drivers/analog.c
@@ -43,7 +43,7 @@
#endif
// Otherwise assume V3
-#if defined(STM32F0XX) || defined(STM32L0XX)
+#if defined(STM32F0XX) || defined(STM32L0XX) || defined(STM32G0XX)
# define USE_ADCV1
#elif defined(STM32F1XX) || defined(STM32F2XX) || defined(STM32F4XX) || defined(GD32VF103) || defined(WB32F3G71xx) || defined(WB32FQ95xx) || defined(AT32F415)
# define USE_ADCV2
@@ -82,7 +82,7 @@
/* User configurable ADC options */
#ifndef ADC_COUNT
-# if defined(RP2040) || defined(STM32F0XX) || defined(STM32F1XX) || defined(STM32F4XX) || defined(GD32VF103) || defined(WB32F3G71xx) || defined(WB32FQ95xx) || defined(AT32F415)
+# if defined(RP2040) || defined(STM32F0XX) || defined(STM32F1XX) || defined(STM32F4XX) || defined(STM32G0XX) || defined(GD32VF103) || defined(WB32F3G71xx) || defined(WB32FQ95xx) || defined(AT32F415)
# define ADC_COUNT 1
# elif defined(STM32F3XX) || defined(STM32G4XX)
# define ADC_COUNT 4
@@ -114,6 +114,8 @@
# define ADC_SAMPLING_RATE ADC_SMPR_SMP_1P5
# elif defined(ADC_SMPR_SMP_2P5) // STM32L4XX, STM32L4XXP, STM32G4XX, STM32WBXX
# define ADC_SAMPLING_RATE ADC_SMPR_SMP_2P5
+# elif defined(ADC_SMPR_SMP1_1P5) // STM32G0XX
+# define ADC_SAMPLING_RATE ADC_SMPR_SMP1_1P5
# else
# error "Cannot determine the default ADC_SAMPLING_RATE for this MCU."
# endif
@@ -293,6 +295,23 @@ __attribute__((weak)) adc_mux pinToMux(pin_t pin) {
case F9: return TO_MUX( ADC_CHANNEL_IN12, 2 );
case F10: return TO_MUX( ADC_CHANNEL_IN13, 2 );
# endif
+#elif defined(STM32G0XX)
+ case A0: return TO_MUX( 0, 0 );
+ case A1: return TO_MUX( 1, 0 );
+ case A2: return TO_MUX( 2, 0 );
+ case A3: return TO_MUX( 3, 0 );
+ case A4: return TO_MUX( 4, 0 );
+ case A5: return TO_MUX( 5, 0 );
+ case A6: return TO_MUX( 6, 0 );
+ case A7: return TO_MUX( 7, 0 );
+ case B0: return TO_MUX( 8, 0 );
+ case B1: return TO_MUX( 9, 0 );
+ case B2: return TO_MUX( 10, 0 );
+ case B10: return TO_MUX( 11, 0 );
+ case B11: return TO_MUX( 15, 0 );
+ case B12: return TO_MUX( 16, 0 );
+ case C4: return TO_MUX( 17, 0 );
+ case C5: return TO_MUX( 18, 0 );
#elif defined(STM32G4XX)
case A0: return TO_MUX( ADC_CHANNEL_IN1, 0 ); // Can also be ADC2
case A1: return TO_MUX( ADC_CHANNEL_IN2, 0 ); // Can also be ADC2
diff --git a/platforms/chibios/drivers/backlight_pwm.c b/platforms/chibios/drivers/backlight_pwm.c
index 25fe7962b0..47ad008415 100644
--- a/platforms/chibios/drivers/backlight_pwm.c
+++ b/platforms/chibios/drivers/backlight_pwm.c
@@ -28,9 +28,9 @@
// Support for pins which are on TIM1_CH1N
#ifdef BACKLIGHT_PWM_COMPLEMENTARY_OUTPUT
# if BACKLIGHT_ON_STATE == 1
-# define PWM_OUTPUT_MODE PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW;
-# else
# define PWM_OUTPUT_MODE PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH;
+# else
+# define PWM_OUTPUT_MODE PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW;
# endif
#else
# if BACKLIGHT_ON_STATE == 1
diff --git a/platforms/chibios/drivers/eeprom/eeprom_stm32_L0_L1.c b/platforms/chibios/drivers/eeprom/eeprom_stm32_L0_L1.c
index 628137a0b3..31062a4816 100644
--- a/platforms/chibios/drivers/eeprom/eeprom_stm32_L0_L1.c
+++ b/platforms/chibios/drivers/eeprom/eeprom_stm32_L0_L1.c
@@ -25,6 +25,7 @@
#define EEPROM_ADDR(offset) (EEPROM_BASE_ADDR + (offset))
#define EEPROM_PTR(offset) ((__IO uint8_t *)EEPROM_ADDR(offset))
#define EEPROM_BYTE(location, offset) (*(EEPROM_PTR(((uint32_t)location) + ((uint32_t)offset))))
+#define EEPROM_WORD(location) (*(__IO uint32_t *)EEPROM_PTR(location))
#define BUFFER_BYTE(buffer, offset) (*(((uint8_t *)buffer) + offset))
@@ -62,12 +63,16 @@ void eeprom_driver_erase(void) {
STM32_L0_L1_EEPROM_Unlock();
for (size_t offset = 0; offset < STM32_ONBOARD_EEPROM_SIZE; offset += sizeof(uint32_t)) {
+#ifdef QMK_MCU_SERIES_STM32L0XX
FLASH->PECR |= FLASH_PECR_ERASE | FLASH_PECR_DATA;
+#endif
- *(__IO uint32_t *)EEPROM_ADDR(offset) = (uint32_t)0;
+ EEPROM_WORD(offset) = (uint32_t)0;
STM32_L0_L1_EEPROM_WaitNotBusy();
+#ifdef QMK_MCU_SERIES_STM32L0XX
FLASH->PECR &= ~(FLASH_PECR_ERASE | FLASH_PECR_DATA);
+#endif
}
STM32_L0_L1_EEPROM_Lock();
@@ -86,17 +91,39 @@ void eeprom_read_block(void *buf, const void *addr, size_t len) {
}
void eeprom_write_block(const void *buf, void *addr, size_t len) {
- STM32_L0_L1_EEPROM_Unlock();
+ // use word-aligned write to overcome issues with writing null bytes
+ uint32_t start_addr = (uint32_t)addr;
+ if (start_addr >= (STM32_ONBOARD_EEPROM_SIZE)) {
+ return;
+ }
+ uint32_t max_len = (STM32_ONBOARD_EEPROM_SIZE)-start_addr;
+ if (len > max_len) {
+ len = max_len;
+ }
+ uint32_t end_addr = start_addr + len;
- for (size_t offset = 0; offset < len; ++offset) {
- // Drop out if we've hit the limit of the EEPROM
- if ((((uint32_t)addr) + offset) >= STM32_ONBOARD_EEPROM_SIZE) {
- break;
+ uint32_t aligned_start = start_addr & ~0x3;
+ uint32_t aligned_end = (end_addr + 3) & ~0x3;
+
+ STM32_L0_L1_EEPROM_Unlock();
+ for (uint32_t word_addr = aligned_start; word_addr < aligned_end; word_addr += 4) {
+ uint32_t existing_word = EEPROM_WORD(word_addr);
+ uint32_t new_word = existing_word;
+
+ // Update the relevant bytes in the word
+ for (int i = 0; i < 4; i++) {
+ uint32_t byte_addr = word_addr + i;
+ if (byte_addr >= start_addr && byte_addr < end_addr) {
+ uint8_t new_byte = BUFFER_BYTE(buf, byte_addr - start_addr);
+ new_word = (new_word & ~(0xFFU << (i * 8))) | ((uint32_t)new_byte << (i * 8));
+ }
}
- STM32_L0_L1_EEPROM_WaitNotBusy();
- EEPROM_BYTE(addr, offset) = BUFFER_BYTE(buf, offset);
+ // Only write if the word has changed
+ if (new_word != existing_word) {
+ STM32_L0_L1_EEPROM_WaitNotBusy();
+ EEPROM_WORD(word_addr) = new_word;
+ }
}
-
STM32_L0_L1_EEPROM_Lock();
}
diff --git a/platforms/chibios/drivers/i2c_master.c b/platforms/chibios/drivers/i2c_master.c
index 1d7fe27633..20850859b5 100644
--- a/platforms/chibios/drivers/i2c_master.c
+++ b/platforms/chibios/drivers/i2c_master.c
@@ -206,4 +206,4 @@ __attribute__((weak)) i2c_status_t i2c_ping_address(uint8_t address, uint16_t ti
// This approach may produce false negative results for I2C devices that do not respond to a register 0 read request.
uint8_t data = 0;
return i2c_read_register(address, 0, &data, sizeof(data), timeout);
-} \ No newline at end of file
+}
diff --git a/platforms/chibios/drivers/usbpd_stm32g4.c b/platforms/chibios/drivers/usbpd_stm32g4.c
index 21b8f6db95..7603b5627b 100644
--- a/platforms/chibios/drivers/usbpd_stm32g4.c
+++ b/platforms/chibios/drivers/usbpd_stm32g4.c
@@ -76,4 +76,4 @@ __attribute__((weak)) usbpd_allowance_t usbpd_get_allowance(void) {
}
return USBPD_500MA;
-} \ No newline at end of file
+}
diff --git a/platforms/chibios/drivers/wear_leveling/wear_leveling_efl.c b/platforms/chibios/drivers/wear_leveling/wear_leveling_efl.c
index fed16d20b1..fec4646a5b 100644
--- a/platforms/chibios/drivers/wear_leveling/wear_leveling_efl.c
+++ b/platforms/chibios/drivers/wear_leveling/wear_leveling_efl.c
@@ -4,6 +4,7 @@
#include <hal.h>
#include "timer.h"
#include "wear_leveling.h"
+#include "wear_leveling_efl_config.h"
#include "wear_leveling_internal.h"
static flash_offset_t base_offset = UINT32_MAX;
diff --git a/platforms/chibios/drivers/wear_leveling/wear_leveling_legacy.c b/platforms/chibios/drivers/wear_leveling/wear_leveling_legacy.c
index 7c6fd2d808..3d2af625ca 100644
--- a/platforms/chibios/drivers/wear_leveling/wear_leveling_legacy.c
+++ b/platforms/chibios/drivers/wear_leveling/wear_leveling_legacy.c
@@ -4,6 +4,7 @@
#include <hal.h>
#include "timer.h"
#include "wear_leveling.h"
+#include "wear_leveling_legacy_config.h"
#include "wear_leveling_internal.h"
#include "legacy_flash_ops.h"
diff --git a/platforms/chibios/drivers/wear_leveling/wear_leveling_rp2040_flash.c b/platforms/chibios/drivers/wear_leveling/wear_leveling_rp2040_flash.c
index 6624c30b5b..2f3c7c58ca 100644
--- a/platforms/chibios/drivers/wear_leveling/wear_leveling_rp2040_flash.c
+++ b/platforms/chibios/drivers/wear_leveling/wear_leveling_rp2040_flash.c
@@ -6,15 +6,18 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <stdbool.h>
+
#include "pico/bootrom.h"
#include "hardware/flash.h"
#include "hardware/sync.h"
#include "hardware/structs/ssi.h"
#include "hardware/structs/ioqspi.h"
-#include <stdbool.h>
+#include "compiler_support.h"
#include "timer.h"
#include "wear_leveling.h"
+#include "wear_leveling_rp2040_flash_config.h"
#include "wear_leveling_internal.h"
#ifndef WEAR_LEVELING_RP2040_FLASH_BULK_COUNT
@@ -177,7 +180,7 @@ bool backing_store_erase(void) {
#endif
// Ensure the backing size can be cleanly subtracted from the flash size without alignment issues.
- _Static_assert((WEAR_LEVELING_BACKING_SIZE) % (FLASH_SECTOR_SIZE) == 0, "Backing size must be a multiple of FLASH_SECTOR_SIZE");
+ STATIC_ASSERT((WEAR_LEVELING_BACKING_SIZE) % (FLASH_SECTOR_SIZE) == 0, "Backing size must be a multiple of FLASH_SECTOR_SIZE");
interrupts = save_and_disable_interrupts();
flash_range_erase((WEAR_LEVELING_RP2040_FLASH_BASE), (WEAR_LEVELING_BACKING_SIZE));