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-rw-r--r--platforms/chibios/boards/BONSAI_C4/configs/board.h2
-rw-r--r--platforms/chibios/boards/BONSAI_C4/configs/config.h2
-rw-r--r--platforms/chibios/boards/BONSAI_C4/configs/halconf.h2
-rw-r--r--platforms/chibios/boards/GENERIC_AT32_F415XX/board/board.c4
-rw-r--r--platforms/chibios/boards/GENERIC_AT32_F415XX/board/board.h28
-rw-r--r--platforms/chibios/boards/GENERIC_AT32_F415XX/configs/config.h4
-rw-r--r--platforms/chibios/boards/GENERIC_AT32_F415XX/configs/mcuconf.h16
-rw-r--r--platforms/chibios/boards/GENERIC_STM32_F405XG/board/board.mk2
-rw-r--r--platforms/chibios/boards/GENERIC_STM32_F407XE/board/board.mk2
-rw-r--r--platforms/chibios/boards/GENERIC_STM32_F407XE/configs/board.h2
-rw-r--r--platforms/chibios/boards/GENERIC_STM32_G0B1XB/board/board.mk12
-rw-r--r--platforms/chibios/boards/GENERIC_STM32_G0B1XB/board/extra.c68
-rw-r--r--platforms/chibios/boards/GENERIC_STM32_G0B1XB/configs/config.h7
-rw-r--r--platforms/chibios/boards/GENERIC_STM32_G0B1XB/configs/mcuconf.h310
-rw-r--r--platforms/chibios/boards/GENERIC_STM32_G474XE/configs/config.h2
-rw-r--r--platforms/chibios/boards/GENERIC_STM32_H723XG/configs/mcuconf.h2
-rw-r--r--platforms/chibios/boards/GENERIC_WB32_F3G71XX/configs/chconf.h2
-rw-r--r--platforms/chibios/boards/GENERIC_WB32_FQ95XX/configs/chconf.h2
-rw-r--r--platforms/chibios/boards/QMK_PROTON_C/configs/chconf.h23
-rw-r--r--platforms/chibios/boards/SIPEED_LONGAN_NANO/configs/chconf.h2
-rw-r--r--platforms/chibios/boards/common/configs/chconf.h23
-rw-r--r--platforms/chibios/boards/common/ld/STM32G0B1xB.ld85
-rw-r--r--platforms/chibios/bootloaders/stm32duino.c2
-rw-r--r--platforms/chibios/bootloaders/uf2boot.c2
-rw-r--r--platforms/chibios/chibios_config.h8
-rw-r--r--platforms/chibios/converters/promicro_to_bonsai_c4/_pin_defs.h2
-rw-r--r--platforms/chibios/converters/promicro_to_bonsai_c4/post_converter.mk2
-rw-r--r--platforms/chibios/converters/promicro_to_promicro_rp2040/pre_converter.mk6
-rw-r--r--platforms/chibios/drivers/analog.c23
-rw-r--r--platforms/chibios/drivers/audio_pwm_hardware.c18
-rw-r--r--platforms/chibios/drivers/backlight_pwm.c4
-rw-r--r--platforms/chibios/drivers/eeprom/eeprom_stm32_L0_L1.c45
-rw-r--r--platforms/chibios/drivers/i2c_master.c45
-rw-r--r--platforms/chibios/drivers/i2c_master.h49
-rw-r--r--platforms/chibios/drivers/spi_master.c43
-rw-r--r--platforms/chibios/drivers/spi_master.h102
-rw-r--r--platforms/chibios/drivers/uart.h200
-rw-r--r--platforms/chibios/drivers/uart_serial.c83
-rw-r--r--platforms/chibios/drivers/uart_sio.c67
-rw-r--r--platforms/chibios/drivers/usbpd_stm32g4.c2
-rw-r--r--platforms/chibios/drivers/wear_leveling/wear_leveling_efl.c1
-rw-r--r--platforms/chibios/drivers/wear_leveling/wear_leveling_legacy.c1
-rw-r--r--platforms/chibios/drivers/wear_leveling/wear_leveling_rp2040_flash.c7
-rw-r--r--platforms/chibios/errno.h13
-rw-r--r--platforms/chibios/mcu_selection.mk35
-rw-r--r--platforms/chibios/platform.c2
-rw-r--r--platforms/chibios/timer.c12
-rw-r--r--platforms/chibios/vendors/RP/RP2040.mk2
48 files changed, 931 insertions, 447 deletions
diff --git a/platforms/chibios/boards/BONSAI_C4/configs/board.h b/platforms/chibios/boards/BONSAI_C4/configs/board.h
index 372b9bb8bc..81c80b2773 100644
--- a/platforms/chibios/boards/BONSAI_C4/configs/board.h
+++ b/platforms/chibios/boards/BONSAI_C4/configs/board.h
@@ -17,4 +17,4 @@
#include_next <board.h>
-#undef STM32_HSE_BYPASS \ No newline at end of file
+#undef STM32_HSE_BYPASS
diff --git a/platforms/chibios/boards/BONSAI_C4/configs/config.h b/platforms/chibios/boards/BONSAI_C4/configs/config.h
index e933cd6fd1..e0e95eda25 100644
--- a/platforms/chibios/boards/BONSAI_C4/configs/config.h
+++ b/platforms/chibios/boards/BONSAI_C4/configs/config.h
@@ -87,4 +87,4 @@
#ifndef USB_VBUS_PIN
# define USB_VBUS_PIN PAL_LINE(GPIOA, 9)
-#endif \ No newline at end of file
+#endif
diff --git a/platforms/chibios/boards/BONSAI_C4/configs/halconf.h b/platforms/chibios/boards/BONSAI_C4/configs/halconf.h
index 6bab6fbcff..55bafe5cfa 100644
--- a/platforms/chibios/boards/BONSAI_C4/configs/halconf.h
+++ b/platforms/chibios/boards/BONSAI_C4/configs/halconf.h
@@ -46,4 +46,4 @@
# define SPI_USE_WAIT TRUE
#endif
-#include_next <halconf.h> \ No newline at end of file
+#include_next <halconf.h>
diff --git a/platforms/chibios/boards/GENERIC_AT32_F415XX/board/board.c b/platforms/chibios/boards/GENERIC_AT32_F415XX/board/board.c
index 28cf7c18e0..26b1974e4a 100644
--- a/platforms/chibios/boards/GENERIC_AT32_F415XX/board/board.c
+++ b/platforms/chibios/boards/GENERIC_AT32_F415XX/board/board.c
@@ -1,7 +1,7 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
- ChibiOS - Copyright (C) 2023..2024 HorrorTroll
- ChibiOS - Copyright (C) 2023..2024 Zhaqian
+ ChibiOS - Copyright (C) 2023..2025 HorrorTroll
+ ChibiOS - Copyright (C) 2023..2025 Zhaqian
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
diff --git a/platforms/chibios/boards/GENERIC_AT32_F415XX/board/board.h b/platforms/chibios/boards/GENERIC_AT32_F415XX/board/board.h
index c3ade198ba..b4909b0a29 100644
--- a/platforms/chibios/boards/GENERIC_AT32_F415XX/board/board.h
+++ b/platforms/chibios/boards/GENERIC_AT32_F415XX/board/board.h
@@ -1,7 +1,7 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
- ChibiOS - Copyright (C) 2023..2024 HorrorTroll
- ChibiOS - Copyright (C) 2023..2024 Zhaqian
+ ChibiOS - Copyright (C) 2023..2025 HorrorTroll
+ ChibiOS - Copyright (C) 2023..2025 Zhaqian
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -50,6 +50,14 @@
#define AT32F415KB
/*
+ * GPIO settings, allow unused GPIO for smaller chip packages.
+ */
+#if defined(AT32F415KB) || defined(AT32F415KC)
+#define AT32_HAS_GPIOC TRUE
+#define AT32_HAS_GPIOF TRUE
+#endif
+
+/*
* IO pins assignments.
*/
#define GPIOA_PIN0 0U
@@ -142,21 +150,21 @@
* 6 - Open Drain output 2MHz.
* 7 - Open Drain output 50MHz.
* 8 - Digital input with Pull-Up or Pull-Down resistor depending on ODT.
- * 9 - Alternate Push Pull output 10MHz.
- * A - Alternate Push Pull output 2MHz.
- * B - Alternate Push Pull output 50MHz.
+ * 9 - Multiplexing Push Pull output 10MHz.
+ * A - Multiplexing Push Pull output 2MHz.
+ * B - Multiplexing Push Pull output 50MHz.
* C - Reserved.
- * D - Alternate Open Drain output 10MHz.
- * E - Alternate Open Drain output 2MHz.
- * F - Alternate Open Drain output 50MHz.
+ * D - Multiplexing Open Drain output 10MHz.
+ * E - Multiplexing Open Drain output 2MHz.
+ * F - Multiplexing Open Drain output 50MHz.
* Please refer to the AT32 Reference Manual for details.
*/
/*
* Port A setup.
*/
-#define VAL_GPIOACFGLR 0x88888B88 /* PA7...PA0 */
-#define VAL_GPIOACFGHR 0x888888B8 /* PA15...PA8 */
+#define VAL_GPIOACFGLR 0x88888888 /* PA7...PA0 */
+#define VAL_GPIOACFGHR 0x88888888 /* PA15...PA8 */
#define VAL_GPIOAODT 0xFFFFFFFF
/*
diff --git a/platforms/chibios/boards/GENERIC_AT32_F415XX/configs/config.h b/platforms/chibios/boards/GENERIC_AT32_F415XX/configs/config.h
index da60447a0a..01d9a47aac 100644
--- a/platforms/chibios/boards/GENERIC_AT32_F415XX/configs/config.h
+++ b/platforms/chibios/boards/GENERIC_AT32_F415XX/configs/config.h
@@ -1,5 +1,5 @@
-// Copyright 2023-2024 HorrorTroll <https://github.com/HorrorTroll>
-// Copyright 2023-2024 Zhaqian <https://github.com/zhaqian12>
+// Copyright 2023-2025 HorrorTroll <https://github.com/HorrorTroll>
+// Copyright 2023-2025 Zhaqian <https://github.com/zhaqian12>
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
diff --git a/platforms/chibios/boards/GENERIC_AT32_F415XX/configs/mcuconf.h b/platforms/chibios/boards/GENERIC_AT32_F415XX/configs/mcuconf.h
index d148379fe1..e218e4791a 100644
--- a/platforms/chibios/boards/GENERIC_AT32_F415XX/configs/mcuconf.h
+++ b/platforms/chibios/boards/GENERIC_AT32_F415XX/configs/mcuconf.h
@@ -1,7 +1,7 @@
/*
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
- ChibiOS - Copyright (C) 2023..2024 HorrorTroll
- ChibiOS - Copyright (C) 2023..2024 Zhaqian
+ ChibiOS - Copyright (C) 2023..2025 HorrorTroll
+ ChibiOS - Copyright (C) 2023..2025 Zhaqian
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -63,7 +63,7 @@
#define AT32_USBDIV AT32_USBDIV_DIV3
#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_NOCLOCK
#define AT32_CLKOUTDIV AT32_CLKOUTDIV_DIV1
-#define AT32_ERTCSEL AT32_ERTCSEL_HEXTDIV
+#define AT32_ERTCSEL AT32_ERTCSEL_NOCLOCK
#define AT32_PVM_ENABLE FALSE
#define AT32_PVMSEL AT32_PVMSEL_LEV1
@@ -136,10 +136,10 @@
#define AT32_I2C_USE_I2C1 FALSE
#define AT32_I2C_USE_I2C2 FALSE
#define AT32_I2C_BUSY_TIMEOUT 50
-#define AT32_I2C_I2C1_IRQ_PRIORITY 5
-#define AT32_I2C_I2C2_IRQ_PRIORITY 5
#define AT32_I2C_I2C1_DMA_PRIORITY 3
#define AT32_I2C_I2C2_DMA_PRIORITY 3
+#define AT32_I2C_I2C1_IRQ_PRIORITY 5
+#define AT32_I2C_I2C2_IRQ_PRIORITY 5
#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
@@ -151,8 +151,6 @@
#define AT32_ICU_USE_TMR4 FALSE
#define AT32_ICU_USE_TMR5 FALSE
#define AT32_ICU_USE_TMR9 FALSE
-#define AT32_ICU_USE_TMR10 FALSE
-#define AT32_ICU_USE_TMR11 FALSE
/*
* PWM driver system settings.
@@ -216,9 +214,13 @@
#define AT32_UART_USE_USART1 FALSE
#define AT32_UART_USE_USART2 FALSE
#define AT32_UART_USE_USART3 FALSE
+#define AT32_UART_USE_UART4 FALSE
+#define AT32_UART_USE_UART5 FALSE
#define AT32_UART_USART1_DMA_PRIORITY 0
#define AT32_UART_USART2_DMA_PRIORITY 0
#define AT32_UART_USART3_DMA_PRIORITY 0
+#define AT32_UART_UART4_DMA_PRIORITY 0
+#define AT32_UART_UART5_DMA_PRIORITY 0
#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
diff --git a/platforms/chibios/boards/GENERIC_STM32_F405XG/board/board.mk b/platforms/chibios/boards/GENERIC_STM32_F405XG/board/board.mk
index 6c837bb8ee..00cc9b20b2 100644
--- a/platforms/chibios/boards/GENERIC_STM32_F405XG/board/board.mk
+++ b/platforms/chibios/boards/GENERIC_STM32_F405XG/board/board.mk
@@ -6,4 +6,4 @@ BOARDINC = $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY
# Shared variables
ALLCSRC += $(BOARDSRC)
-ALLINC += $(BOARDINC) \ No newline at end of file
+ALLINC += $(BOARDINC)
diff --git a/platforms/chibios/boards/GENERIC_STM32_F407XE/board/board.mk b/platforms/chibios/boards/GENERIC_STM32_F407XE/board/board.mk
index 6c837bb8ee..00cc9b20b2 100644
--- a/platforms/chibios/boards/GENERIC_STM32_F407XE/board/board.mk
+++ b/platforms/chibios/boards/GENERIC_STM32_F407XE/board/board.mk
@@ -6,4 +6,4 @@ BOARDINC = $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY
# Shared variables
ALLCSRC += $(BOARDSRC)
-ALLINC += $(BOARDINC) \ No newline at end of file
+ALLINC += $(BOARDINC)
diff --git a/platforms/chibios/boards/GENERIC_STM32_F407XE/configs/board.h b/platforms/chibios/boards/GENERIC_STM32_F407XE/configs/board.h
index a0d53d86e7..c2f25db810 100644
--- a/platforms/chibios/boards/GENERIC_STM32_F407XE/configs/board.h
+++ b/platforms/chibios/boards/GENERIC_STM32_F407XE/configs/board.h
@@ -21,4 +21,4 @@
#include_next <board.h>
-#undef STM32_HSE_BYPASS \ No newline at end of file
+#undef STM32_HSE_BYPASS
diff --git a/platforms/chibios/boards/GENERIC_STM32_G0B1XB/board/board.mk b/platforms/chibios/boards/GENERIC_STM32_G0B1XB/board/board.mk
new file mode 100644
index 0000000000..7e551e4dc7
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_STM32_G0B1XB/board/board.mk
@@ -0,0 +1,12 @@
+# List of all the board related files.
+BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_G0B1RE/board.c
+
+# Extra files
+BOARDSRC += $(BOARD_PATH)/board/extra.c
+
+# Required include directories
+BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_G0B1RE
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC += $(BOARDINC)
diff --git a/platforms/chibios/boards/GENERIC_STM32_G0B1XB/board/extra.c b/platforms/chibios/boards/GENERIC_STM32_G0B1XB/board/extra.c
new file mode 100644
index 0000000000..4dbc5dd8b4
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_STM32_G0B1XB/board/extra.c
@@ -0,0 +1,68 @@
+// Copyright 2025 Stefan Kerkmann (@karlk90)
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <hal.h>
+
+#define FLASH_KEY1 0x45670123U
+#define FLASH_KEY2 0xCDEF89ABU
+#define FLASH_OPTKEY1 0x08192A3BU
+#define FLASH_OPTKEY2 0x4C5D6E7FU
+#define FLASH_OPTR_CLR_MASK (FLASH_OPTR_nBOOT_SEL)
+#define FLASH_OPTR_SET_MASK (FLASH_OPTR_NRST_MODE_Msk)
+
+static void wait_for_flash(void) {
+ while (READ_BIT(FLASH->SR, FLASH_SR_BSY1)) {
+ }
+}
+
+void __attribute__((constructor)) enable_boot0_and_nrst_pin(void) {
+ // Only apply on STM32G0x1 devices, see RM0444 Rev 6, Table 265: "DEV_ID
+ // and REV_ID field values."
+ switch (READ_BIT(DBG->IDCODE, DBG_IDCODE_DEV_ID)) {
+ case 0x467: // STM32G0B1xx and STM32G0C1xx
+ case 0x460: // STM32G071xx and STM32G081xx
+ case 0x456: // STM32G051xx and STM32G061xx
+ case 0x466: // STM32G041xx and STM32G031xx
+ break;
+ default:
+ return;
+ }
+
+ uint32_t optr = FLASH->OPTR;
+
+ // Make sure that:
+ // 1. legacy boot0 pin handling is enabled.
+ // OPTR[24] = 0
+ // 2. legacy nRST pin handling is enabled.
+ // OPTR[28:27] = 0b11
+ // To match the default behavior found in older (F0/F1/F3/F4) STM32 devices.
+ if (READ_BIT(optr, FLASH_OPTR_CLR_MASK) || (READ_BIT(optr, FLASH_OPTR_SET_MASK) != FLASH_OPTR_SET_MASK)) {
+ if (READ_BIT(FLASH->CR, FLASH_CR_LOCK)) {
+ WRITE_REG(FLASH->KEYR, FLASH_KEY1);
+ WRITE_REG(FLASH->KEYR, FLASH_KEY2);
+ while (READ_BIT(FLASH->CR, FLASH_CR_LOCK)) {
+ }
+ wait_for_flash();
+ }
+ if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK)) {
+ WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
+ WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
+ while (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK)) {
+ }
+ wait_for_flash();
+ }
+
+ MODIFY_REG(FLASH->OPTR, FLASH_OPTR_CLR_MASK, FLASH_OPTR_SET_MASK);
+ wait_for_flash();
+
+ SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+ wait_for_flash();
+
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+ wait_for_flash();
+
+ // Launch the option byte (re)loading, which resets the device. This
+ // should not return.
+ SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
+ }
+}
diff --git a/platforms/chibios/boards/GENERIC_STM32_G0B1XB/configs/config.h b/platforms/chibios/boards/GENERIC_STM32_G0B1XB/configs/config.h
new file mode 100644
index 0000000000..bb2d1b5816
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_STM32_G0B1XB/configs/config.h
@@ -0,0 +1,7 @@
+// Copyright 2024 Stefan Kerkmann (@karlk90)
+// SPDX-License-Identifier: GPL-2.0-or-later
+#pragma once
+
+#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
+# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
+#endif
diff --git a/platforms/chibios/boards/GENERIC_STM32_G0B1XB/configs/mcuconf.h b/platforms/chibios/boards/GENERIC_STM32_G0B1XB/configs/mcuconf.h
new file mode 100644
index 0000000000..80726e0308
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_STM32_G0B1XB/configs/mcuconf.h
@@ -0,0 +1,310 @@
+/*
+ ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32G0xx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 3...0 Lowest...Highest.
+ *
+ * DMA priorities:
+ * 0...3 Lowest...Highest.
+ */
+
+#ifndef MCUCONF_H
+#define MCUCONF_H
+
+#define STM32G0xx_MCUCONF
+#define STM32G0B1_MCUCONF
+#define STM32G0C1_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define STM32_NO_INIT FALSE
+#define STM32_CLOCK_DYNAMIC TRUE
+#define STM32_VOS STM32_VOS_RANGE1
+#define STM32_PWR_CR2 (STM32_PVDRT_LEV0 | STM32_PVDFT_LEV0 | STM32_PVDE_DISABLED)
+#define STM32_PWR_CR3 (PWR_CR3_EIWUL)
+#define STM32_PWR_CR4 (0U)
+#define STM32_PWR_PUCRA (0U)
+#define STM32_PWR_PDCRA (0U)
+#define STM32_PWR_PUCRB (0U)
+#define STM32_PWR_PDCRB (0U)
+#define STM32_PWR_PUCRC (0U)
+#define STM32_PWR_PDCRC (0U)
+#define STM32_PWR_PUCRD (0U)
+#define STM32_PWR_PDCRD (0U)
+#define STM32_PWR_PUCRE (0U)
+#define STM32_PWR_PDCRE (0U)
+#define STM32_PWR_PUCRF (0U)
+#define STM32_PWR_PDCRF (0U)
+#define STM32_HSIDIV_VALUE 1
+#define STM32_HSI16_ENABLED TRUE
+#define STM32_HSI48_ENABLED TRUE
+#define STM32_HSE_ENABLED FALSE
+#define STM32_LSI_ENABLED FALSE
+#define STM32_LSE_ENABLED FALSE
+#define STM32_SW STM32_SW_PLLRCLK
+#define STM32_PLLSRC STM32_PLLSRC_HSI16
+#define STM32_PLLM_VALUE 2
+#define STM32_PLLN_VALUE 16
+#define STM32_PLLP_VALUE 2
+#define STM32_PLLQ_VALUE 4
+#define STM32_PLLR_VALUE 2
+#define STM32_HPRE STM32_HPRE_DIV1
+#define STM32_PPRE STM32_PPRE_DIV1
+#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
+#define STM32_MCOPRE STM32_MCOPRE_DIV1
+#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
+
+/*
+ * Peripherals clocks and sources.
+ */
+#define STM32_FDCANSEL STM32_USBSEL_HSI48
+#define STM32_USBSEL STM32_USBSEL_HSI48
+#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
+#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
+#define STM32_USART3SEL STM32_USART3SEL_SYSCLK
+#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
+#define STM32_LPUART2SEL STM32_LPUART2SEL_SYSCLK
+#define STM32_CECSEL STM32_CECSEL_HSI16DIV
+#define STM32_I2C1SEL STM32_I2C1SEL_PCLK
+#define STM32_I2C2SEL STM32_I2C1SEL_PCLK
+#define STM32_I2S1SEL STM32_I2S1SEL_SYSCLK
+#define STM32_I2S2SEL STM32_I2S2SEL_SYSCLK
+#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK
+#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK
+#define STM32_TIM1SEL STM32_TIM1SEL_TIMPCLK
+#define STM32_TIM15SEL STM32_TIM15SEL_TIMPCLK
+#define STM32_RNGSEL STM32_RNGSEL_HSI16
+#define STM32_RNGDIV_VALUE 1
+#define STM32_ADCSEL STM32_ADCSEL_PLLPCLK
+#define STM32_RTCSEL STM32_RTCSEL_NOCLOCK
+
+/*
+ * Shared IRQ settings.
+ */
+#define STM32_IRQ_EXTI0_1_PRIORITY 3
+#define STM32_IRQ_EXTI2_3_PRIORITY 3
+#define STM32_IRQ_EXTI4_15_PRIORITY 3
+#define STM32_IRQ_EXTI1921_PRIORITY 3
+
+#define STM32_IRQ_USART1_PRIORITY 2
+#define STM32_IRQ_USART2_LP2_PRIORITY 2
+#define STM32_IRQ_USART3_4_5_6_LP1_PRIORITY 2
+
+#define STM32_IRQ_TIM1_UP_PRIORITY 1
+#define STM32_IRQ_TIM1_CC_PRIORITY 1
+#define STM32_IRQ_TIM2_PRIORITY 1
+#define STM32_IRQ_TIM3_4_PRIORITY 1
+#define STM32_IRQ_TIM6_PRIORITY 1
+#define STM32_IRQ_TIM7_PRIORITY 1
+#define STM32_IRQ_TIM14_PRIORITY 1
+#define STM32_IRQ_TIM15_PRIORITY 1
+#define STM32_IRQ_TIM16_PRIORITY 1
+#define STM32_IRQ_TIM17_PRIORITY 1
+
+/*
+ * ADC driver system settings.
+ */
+#define STM32_ADC_USE_ADC1 FALSE
+#define STM32_ADC_ADC1_CFGR2 ADC_CFGR2_CKMODE_ADCCLK
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_ADC_PRESCALER_VALUE 2
+
+/*
+ * DAC driver system settings.
+ */
+#define STM32_DAC_DUAL_MODE FALSE
+#define STM32_DAC_USE_DAC1_CH1 FALSE
+#define STM32_DAC_USE_DAC1_CH2 FALSE
+#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 3
+#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 3
+#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
+#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+
+/*
+ * GPT driver system settings.
+ */
+#define STM32_GPT_USE_TIM1 FALSE
+#define STM32_GPT_USE_TIM2 FALSE
+#define STM32_GPT_USE_TIM3 FALSE
+#define STM32_GPT_USE_TIM4 FALSE
+#define STM32_GPT_USE_TIM6 FALSE
+#define STM32_GPT_USE_TIM7 FALSE
+#define STM32_GPT_USE_TIM14 FALSE
+#define STM32_GPT_USE_TIM15 FALSE
+#define STM32_GPT_USE_TIM16 FALSE
+#define STM32_GPT_USE_TIM17 FALSE
+
+/*
+ * I2C driver system settings.
+ */
+#define STM32_I2C_USE_I2C1 FALSE
+#define STM32_I2C_USE_I2C2 FALSE
+#define STM32_I2C_USE_I2C3 FALSE
+#define STM32_I2C_BUSY_TIMEOUT 50
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C1_IRQ_PRIORITY 3
+#define STM32_I2C_I2C2_IRQ_PRIORITY 3
+#define STM32_I2C_I2C1_DMA_PRIORITY 3
+#define STM32_I2C_I2C2_DMA_PRIORITY 3
+#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
+
+/*
+ * ICU driver system settings.
+ */
+#define STM32_ICU_USE_TIM1 FALSE
+#define STM32_ICU_USE_TIM2 FALSE
+#define STM32_ICU_USE_TIM3 FALSE
+#define STM32_ICU_USE_TIM4 FALSE
+#define STM32_ICU_USE_TIM15 FALSE
+
+/*
+ * PWM driver system settings.
+ */
+#define STM32_PWM_USE_TIM1 FALSE
+#define STM32_PWM_USE_TIM2 FALSE
+#define STM32_PWM_USE_TIM3 FALSE
+#define STM32_PWM_USE_TIM4 FALSE
+#define STM32_PWM_USE_TIM14 FALSE
+#define STM32_PWM_USE_TIM15 FALSE
+#define STM32_PWM_USE_TIM16 FALSE
+#define STM32_PWM_USE_TIM17 FALSE
+
+/*
+ * RTC driver system settings.
+ */
+#define STM32_RTC_PRESA_VALUE 32
+#define STM32_RTC_PRESS_VALUE 1024
+#define STM32_RTC_CR_INIT 0
+#define STM32_RTC_TAMPCR_INIT 0
+
+/*
+ * SERIAL driver system settings.
+ */
+#define STM32_SERIAL_USE_USART1 FALSE
+#define STM32_SERIAL_USE_USART2 FALSE
+#define STM32_SERIAL_USE_USART3 FALSE
+#define STM32_SERIAL_USE_UART4 FALSE
+#define STM32_SERIAL_USE_UART5 FALSE
+#define STM32_SERIAL_USE_USART6 FALSE
+#define STM32_SERIAL_USE_LPUART1 FALSE
+#define STM32_SERIAL_USE_LPUART2 FALSE
+
+/*
+ * SIO driver system settings.
+ */
+#define STM32_SIO_USE_USART1 FALSE
+#define STM32_SIO_USE_USART2 FALSE
+#define STM32_SIO_USE_USART3 FALSE
+#define STM32_SIO_USE_UART4 FALSE
+#define STM32_SIO_USE_UART5 FALSE
+#define STM32_SIO_USE_USART6 FALSE
+#define STM32_SIO_USE_LPUART1 FALSE
+#define STM32_SIO_USE_LPUART2 FALSE
+
+/*
+ * SPI driver system settings.
+ */
+#define STM32_SPI_USE_SPI1 FALSE
+#define STM32_SPI_USE_SPI2 FALSE
+#define STM32_SPI_USE_SPI3 FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI1_DMA_PRIORITY 1
+#define STM32_SPI_SPI2_DMA_PRIORITY 1
+#define STM32_SPI_SPI3_DMA_PRIORITY 1
+#define STM32_SPI_SPI1_IRQ_PRIORITY 2
+#define STM32_SPI_SPI2_IRQ_PRIORITY 2
+#define STM32_SPI_SPI3_IRQ_PRIORITY 2
+#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
+
+/*
+ * ST driver system settings.
+ */
+#define STM32_ST_IRQ_PRIORITY 2
+#define STM32_ST_USE_TIMER 2
+
+/*
+ * TRNG driver system settings.
+ * NOTE: STM32G0C1 only.
+ */
+#define STM32_TRNG_USE_RNG1 FALSE
+
+/*
+ * UART driver system settings.
+ */
+#define STM32_UART_USE_USART1 FALSE
+#define STM32_UART_USE_USART2 FALSE
+#define STM32_UART_USE_USART3 FALSE
+#define STM32_UART_USE_UART4 FALSE
+#define STM32_UART_USE_UART5 FALSE
+#define STM32_UART_USE_USART6 FALSE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART1_DMA_PRIORITY 0
+#define STM32_UART_USART2_DMA_PRIORITY 0
+#define STM32_UART_USART3_DMA_PRIORITY 0
+#define STM32_UART_UART4_DMA_PRIORITY 0
+#define STM32_UART_UART5_DMA_PRIORITY 0
+#define STM32_UART_USART6_DMA_PRIORITY 0
+#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
+
+/*
+ * USB driver system settings.
+ */
+#define STM32_USB_USE_USB1 TRUE
+#define STM32_USB_USB1_LP_IRQ_PRIORITY 3
+#define STM32_USB_USE_ISOCHRONOUS FALSE
+#define STM32_USB_USE_FAST_COPY TRUE
+#define STM32_USB_HOST_WAKEUP_DURATION 2
+#define STM32_USB_48MHZ_DELTA 0
+
+/*
+ * WDG driver system settings.
+ */
+#define STM32_WDG_USE_IWDG FALSE
+
+#endif /* MCUCONF_H */
diff --git a/platforms/chibios/boards/GENERIC_STM32_G474XE/configs/config.h b/platforms/chibios/boards/GENERIC_STM32_G474XE/configs/config.h
index eb74d68e85..da0a634bb5 100644
--- a/platforms/chibios/boards/GENERIC_STM32_G474XE/configs/config.h
+++ b/platforms/chibios/boards/GENERIC_STM32_G474XE/configs/config.h
@@ -27,4 +27,4 @@
#if 0
#define STM32_BOOTLOADER_DUAL_BANK TRUE
#define STM32_BOOTLOADER_DUAL_BANK_GPIO B7
-#endif \ No newline at end of file
+#endif
diff --git a/platforms/chibios/boards/GENERIC_STM32_H723XG/configs/mcuconf.h b/platforms/chibios/boards/GENERIC_STM32_H723XG/configs/mcuconf.h
index 0239ec5273..09096c3977 100644
--- a/platforms/chibios/boards/GENERIC_STM32_H723XG/configs/mcuconf.h
+++ b/platforms/chibios/boards/GENERIC_STM32_H723XG/configs/mcuconf.h
@@ -182,6 +182,7 @@
#define STM32_IRQ_FDCAN1_PRIORITY 10
#define STM32_IRQ_FDCAN2_PRIORITY 10
+#define STM32_IRQ_FDCAN3_PRIORITY 10
#define STM32_IRQ_MDMA_PRIORITY 9
@@ -235,6 +236,7 @@
*/
#define STM32_CAN_USE_FDCAN1 FALSE
#define STM32_CAN_USE_FDCAN2 FALSE
+#define STM32_CAN_USE_FDCAN3 FALSE
/*
* DAC driver system settings.
diff --git a/platforms/chibios/boards/GENERIC_WB32_F3G71XX/configs/chconf.h b/platforms/chibios/boards/GENERIC_WB32_F3G71XX/configs/chconf.h
index e4afddb6a5..fa0b6f11d0 100644
--- a/platforms/chibios/boards/GENERIC_WB32_F3G71XX/configs/chconf.h
+++ b/platforms/chibios/boards/GENERIC_WB32_F3G71XX/configs/chconf.h
@@ -23,4 +23,4 @@
#define CH_CFG_ST_TIMEDELTA 0
-#include_next <chconf.h> \ No newline at end of file
+#include_next <chconf.h>
diff --git a/platforms/chibios/boards/GENERIC_WB32_FQ95XX/configs/chconf.h b/platforms/chibios/boards/GENERIC_WB32_FQ95XX/configs/chconf.h
index e4afddb6a5..fa0b6f11d0 100644
--- a/platforms/chibios/boards/GENERIC_WB32_FQ95XX/configs/chconf.h
+++ b/platforms/chibios/boards/GENERIC_WB32_FQ95XX/configs/chconf.h
@@ -23,4 +23,4 @@
#define CH_CFG_ST_TIMEDELTA 0
-#include_next <chconf.h> \ No newline at end of file
+#include_next <chconf.h>
diff --git a/platforms/chibios/boards/QMK_PROTON_C/configs/chconf.h b/platforms/chibios/boards/QMK_PROTON_C/configs/chconf.h
index cc10304a3f..e92b7aeb98 100644
--- a/platforms/chibios/boards/QMK_PROTON_C/configs/chconf.h
+++ b/platforms/chibios/boards/QMK_PROTON_C/configs/chconf.h
@@ -49,6 +49,19 @@
#define CH_CFG_SMP_MODE FALSE
#endif
+/**
+ * @brief Kernel hardening level.
+ * @details This option is the level of functional-safety checks enabled
+ * in the kerkel. The meaning is:
+ * - 0: No checks, maximum performance.
+ * - 1: Reasonable checks.
+ * - 2: All checks.
+ * .
+ */
+#if !defined(CH_CFG_HARDENING_LEVEL)
+#define CH_CFG_HARDENING_LEVEL 0
+#endif
+
/** @} */
/*===========================================================================*/
@@ -361,6 +374,16 @@
#endif
/**
+ * @brief Memory checks APIs.
+ * @details If enabled then the memory checks APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_USE_MEMCHECKS)
+#define CH_CFG_USE_MEMCHECKS TRUE
+#endif
+
+/**
* @brief Core Memory Manager APIs.
* @details If enabled then the core memory manager APIs are included
* in the kernel.
diff --git a/platforms/chibios/boards/SIPEED_LONGAN_NANO/configs/chconf.h b/platforms/chibios/boards/SIPEED_LONGAN_NANO/configs/chconf.h
index 6e5adb0fe1..ca0348e4e0 100644
--- a/platforms/chibios/boards/SIPEED_LONGAN_NANO/configs/chconf.h
+++ b/platforms/chibios/boards/SIPEED_LONGAN_NANO/configs/chconf.h
@@ -20,4 +20,4 @@
struct _reent;
#endif
-#include_next <chconf.h> \ No newline at end of file
+#include_next <chconf.h>
diff --git a/platforms/chibios/boards/common/configs/chconf.h b/platforms/chibios/boards/common/configs/chconf.h
index 5db836e37c..6381298ef7 100644
--- a/platforms/chibios/boards/common/configs/chconf.h
+++ b/platforms/chibios/boards/common/configs/chconf.h
@@ -49,6 +49,19 @@
#define CH_CFG_SMP_MODE FALSE
#endif
+/**
+ * @brief Kernel hardening level.
+ * @details This option is the level of functional-safety checks enabled
+ * in the kerkel. The meaning is:
+ * - 0: No checks, maximum performance.
+ * - 1: Reasonable checks.
+ * - 2: All checks.
+ * .
+ */
+#if !defined(CH_CFG_HARDENING_LEVEL)
+#define CH_CFG_HARDENING_LEVEL 0
+#endif
+
/** @} */
/*===========================================================================*/
@@ -361,6 +374,16 @@
#endif
/**
+ * @brief Memory checks APIs.
+ * @details If enabled then the memory checks APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_USE_MEMCHECKS)
+#define CH_CFG_USE_MEMCHECKS TRUE
+#endif
+
+/**
* @brief Core Memory Manager APIs.
* @details If enabled then the core memory manager APIs are included
* in the kernel.
diff --git a/platforms/chibios/boards/common/ld/STM32G0B1xB.ld b/platforms/chibios/boards/common/ld/STM32G0B1xB.ld
new file mode 100644
index 0000000000..0109504992
--- /dev/null
+++ b/platforms/chibios/boards/common/ld/STM32G0B1xB.ld
@@ -0,0 +1,85 @@
+/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32G0B1xB memory setup.
+ */
+MEMORY
+{
+ flash0 (rx) : org = 0x08000000, len = 128k
+ flash1 (rx) : org = 0x00000000, len = 0
+ flash2 (rx) : org = 0x00000000, len = 0
+ flash3 (rx) : org = 0x00000000, len = 0
+ flash4 (rx) : org = 0x00000000, len = 0
+ flash5 (rx) : org = 0x00000000, len = 0
+ flash6 (rx) : org = 0x00000000, len = 0
+ flash7 (rx) : org = 0x00000000, len = 0
+ ram0 (wx) : org = 0x20000000, len = 144k
+ ram1 (wx) : org = 0x00000000, len = 0
+ ram2 (wx) : org = 0x00000000, len = 0
+ ram3 (wx) : org = 0x00000000, len = 0
+ ram4 (wx) : org = 0x00000000, len = 0
+ ram5 (wx) : org = 0x00000000, len = 0
+ ram6 (wx) : org = 0x00000000, len = 0
+ ram7 (wx) : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/platforms/chibios/bootloaders/stm32duino.c b/platforms/chibios/bootloaders/stm32duino.c
index e2db7fa16c..cc3f6be2df 100644
--- a/platforms/chibios/bootloaders/stm32duino.c
+++ b/platforms/chibios/bootloaders/stm32duino.c
@@ -25,4 +25,4 @@ __attribute__((weak)) void bootloader_jump(void) {
__attribute__((weak)) void mcu_reset(void) {
BKP->DR10 = RTC_BOOTLOADER_JUST_UPLOADED;
NVIC_SystemReset();
-} \ No newline at end of file
+}
diff --git a/platforms/chibios/bootloaders/uf2boot.c b/platforms/chibios/bootloaders/uf2boot.c
index f5b1a64334..1c736b8356 100644
--- a/platforms/chibios/bootloaders/uf2boot.c
+++ b/platforms/chibios/bootloaders/uf2boot.c
@@ -1,6 +1,8 @@
// Copyright 2023 QMK
// SPDX-License-Identifier: GPL-2.0-or-later
+#include <stdint.h>
+#include <hal.h>
#include "bootloader.h"
// From mmoskal/uf2-stm32f103's backup.c
diff --git a/platforms/chibios/chibios_config.h b/platforms/chibios/chibios_config.h
index 95136baf30..41546e3e50 100644
--- a/platforms/chibios/chibios_config.h
+++ b/platforms/chibios/chibios_config.h
@@ -15,6 +15,8 @@
*/
#pragma once
+#include "compiler_support.h"
+
#ifndef USB_VBUS_PIN
# define SPLIT_USB_DETECT // Force this on when dedicated pin is not used
#endif
@@ -26,7 +28,7 @@
# define REALTIME_COUNTER_CLOCK 1000000
# define USE_GPIOV1
-# define PAL_OUTPUT_TYPE_OPENDRAIN _Static_assert(0, "RP2040 has no Open Drain GPIO configuration, setting this is not possible");
+# define PAL_OUTPUT_TYPE_OPENDRAIN STATIC_ASSERT(0, "RP2040 has no Open Drain GPIO configuration, setting this is not possible");
/* Aliases for GPIO PWM channels - every pin has at least one PWM channel
* assigned */
@@ -149,8 +151,8 @@
# if defined(AT32F415)
# define USE_GPIOV1
# define USE_I2CV1
-# define PAL_MODE_ALTERNATE_OPENDRAIN PAL_MODE_AT32_ALTERNATE_OPENDRAIN
-# define PAL_MODE_ALTERNATE_PUSHPULL PAL_MODE_AT32_ALTERNATE_PUSHPULL
+# define PAL_MODE_ALTERNATE_OPENDRAIN PAL_MODE_AT32_MUX_OPENDRAIN
+# define PAL_MODE_ALTERNATE_PUSHPULL PAL_MODE_AT32_MUX_PUSHPULL
# define AUDIO_PWM_PAL_MODE PAL_MODE_ALTERNATE_PUSHPULL
# endif
#endif
diff --git a/platforms/chibios/converters/promicro_to_bonsai_c4/_pin_defs.h b/platforms/chibios/converters/promicro_to_bonsai_c4/_pin_defs.h
index 7e6b8ddaf2..deb0628ef8 100644
--- a/platforms/chibios/converters/promicro_to_bonsai_c4/_pin_defs.h
+++ b/platforms/chibios/converters/promicro_to_bonsai_c4/_pin_defs.h
@@ -37,4 +37,4 @@
// If this is undesirable, either B0 or B5 can be redefined by
// using #undef and #define to change its assignment
#define B0 PAL_LINE(GPIOB, 2)
-#define D5 PAL_LINE(GPIOB, 2) \ No newline at end of file
+#define D5 PAL_LINE(GPIOB, 2)
diff --git a/platforms/chibios/converters/promicro_to_bonsai_c4/post_converter.mk b/platforms/chibios/converters/promicro_to_bonsai_c4/post_converter.mk
index 5f49b17f8a..beefb9de23 100644
--- a/platforms/chibios/converters/promicro_to_bonsai_c4/post_converter.mk
+++ b/platforms/chibios/converters/promicro_to_bonsai_c4/post_converter.mk
@@ -2,4 +2,4 @@ BACKLIGHT_DRIVER ?= pwm
WS2812_DRIVER ?= pwm
SERIAL_DRIVER ?= usart
FLASH_DRIVER ?= spi
-EEPROM_DRIVER ?= spi \ No newline at end of file
+EEPROM_DRIVER ?= spi
diff --git a/platforms/chibios/converters/promicro_to_promicro_rp2040/pre_converter.mk b/platforms/chibios/converters/promicro_to_promicro_rp2040/pre_converter.mk
index 303d3135ce..80111d0f78 100644
--- a/platforms/chibios/converters/promicro_to_promicro_rp2040/pre_converter.mk
+++ b/platforms/chibios/converters/promicro_to_promicro_rp2040/pre_converter.mk
@@ -1,2 +1,8 @@
CONVERTER:=platforms/chibios/converters/promicro_to_sparkfun_pm2040
ACTIVE_CONVERTER:=sparkfun_pm2040
+
+$(info @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@)
+$(info The 'CONVERT_TO=promicro_rp2040' option is now deprecated.)
+$(info Depending on hardware either 'CONVERT_TO=sparkfun_pm2040' or 'CONVERT_TO=rp2040_ce' should be used instead.)
+$(info See https://docs.qmk.fm/feature_converters#pro-micro documentation for more information.)
+$(info @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@)
diff --git a/platforms/chibios/drivers/analog.c b/platforms/chibios/drivers/analog.c
index 7e1f87e6c9..a916cc9a1d 100644
--- a/platforms/chibios/drivers/analog.c
+++ b/platforms/chibios/drivers/analog.c
@@ -43,7 +43,7 @@
#endif
// Otherwise assume V3
-#if defined(STM32F0XX) || defined(STM32L0XX)
+#if defined(STM32F0XX) || defined(STM32L0XX) || defined(STM32G0XX)
# define USE_ADCV1
#elif defined(STM32F1XX) || defined(STM32F2XX) || defined(STM32F4XX) || defined(GD32VF103) || defined(WB32F3G71xx) || defined(WB32FQ95xx) || defined(AT32F415)
# define USE_ADCV2
@@ -82,7 +82,7 @@
/* User configurable ADC options */
#ifndef ADC_COUNT
-# if defined(RP2040) || defined(STM32F0XX) || defined(STM32F1XX) || defined(STM32F4XX) || defined(GD32VF103) || defined(WB32F3G71xx) || defined(WB32FQ95xx) || defined(AT32F415)
+# if defined(RP2040) || defined(STM32F0XX) || defined(STM32F1XX) || defined(STM32F4XX) || defined(STM32G0XX) || defined(GD32VF103) || defined(WB32F3G71xx) || defined(WB32FQ95xx) || defined(AT32F415)
# define ADC_COUNT 1
# elif defined(STM32F3XX) || defined(STM32G4XX)
# define ADC_COUNT 4
@@ -114,6 +114,8 @@
# define ADC_SAMPLING_RATE ADC_SMPR_SMP_1P5
# elif defined(ADC_SMPR_SMP_2P5) // STM32L4XX, STM32L4XXP, STM32G4XX, STM32WBXX
# define ADC_SAMPLING_RATE ADC_SMPR_SMP_2P5
+# elif defined(ADC_SMPR_SMP1_1P5) // STM32G0XX
+# define ADC_SAMPLING_RATE ADC_SMPR_SMP1_1P5
# else
# error "Cannot determine the default ADC_SAMPLING_RATE for this MCU."
# endif
@@ -293,6 +295,23 @@ __attribute__((weak)) adc_mux pinToMux(pin_t pin) {
case F9: return TO_MUX( ADC_CHANNEL_IN12, 2 );
case F10: return TO_MUX( ADC_CHANNEL_IN13, 2 );
# endif
+#elif defined(STM32G0XX)
+ case A0: return TO_MUX( 0, 0 );
+ case A1: return TO_MUX( 1, 0 );
+ case A2: return TO_MUX( 2, 0 );
+ case A3: return TO_MUX( 3, 0 );
+ case A4: return TO_MUX( 4, 0 );
+ case A5: return TO_MUX( 5, 0 );
+ case A6: return TO_MUX( 6, 0 );
+ case A7: return TO_MUX( 7, 0 );
+ case B0: return TO_MUX( 8, 0 );
+ case B1: return TO_MUX( 9, 0 );
+ case B2: return TO_MUX( 10, 0 );
+ case B10: return TO_MUX( 11, 0 );
+ case B11: return TO_MUX( 15, 0 );
+ case B12: return TO_MUX( 16, 0 );
+ case C4: return TO_MUX( 17, 0 );
+ case C5: return TO_MUX( 18, 0 );
#elif defined(STM32G4XX)
case A0: return TO_MUX( ADC_CHANNEL_IN1, 0 ); // Can also be ADC2
case A1: return TO_MUX( ADC_CHANNEL_IN2, 0 ); // Can also be ADC2
diff --git a/platforms/chibios/drivers/audio_pwm_hardware.c b/platforms/chibios/drivers/audio_pwm_hardware.c
index 1ba7ec13bc..afa341abb6 100644
--- a/platforms/chibios/drivers/audio_pwm_hardware.c
+++ b/platforms/chibios/drivers/audio_pwm_hardware.c
@@ -41,18 +41,19 @@ static float channel_1_frequency = 0.0f;
void channel_1_set_frequency(float freq) {
channel_1_frequency = freq;
+ pwmcnt_t period;
+ pwmcnt_t width;
if (freq <= 0.0) {
- // a pause/rest has freq=0
- return;
+ period = 2;
+ width = 0;
+ } else {
+ period = (pwmCFG.frequency / freq);
+ width = (pwmcnt_t)(((period) * (pwmcnt_t)((100 - note_timbre) * 100)) / (pwmcnt_t)(10000));
}
-
- pwmcnt_t period = (pwmCFG.frequency / freq);
chSysLockFromISR();
pwmChangePeriodI(&AUDIO_PWM_DRIVER, period);
- pwmEnableChannelI(&AUDIO_PWM_DRIVER, AUDIO_PWM_CHANNEL - 1,
- // adjust the duty-cycle so that the output is for 'note_timbre' duration HIGH
- PWM_PERCENTAGE_TO_WIDTH(&AUDIO_PWM_DRIVER, (100 - note_timbre) * 100));
+ pwmEnableChannelI(&AUDIO_PWM_DRIVER, AUDIO_PWM_CHANNEL - 1, width);
chSysUnlockFromISR();
}
@@ -67,6 +68,9 @@ void channel_1_start(void) {
void channel_1_stop(void) {
pwmStop(&AUDIO_PWM_DRIVER);
+ pwmStart(&AUDIO_PWM_DRIVER, &pwmCFG);
+ pwmEnableChannel(&AUDIO_PWM_DRIVER, AUDIO_PWM_CHANNEL - 1, 0);
+ pwmStop(&AUDIO_PWM_DRIVER);
}
static virtual_timer_t audio_vt;
diff --git a/platforms/chibios/drivers/backlight_pwm.c b/platforms/chibios/drivers/backlight_pwm.c
index 25fe7962b0..47ad008415 100644
--- a/platforms/chibios/drivers/backlight_pwm.c
+++ b/platforms/chibios/drivers/backlight_pwm.c
@@ -28,9 +28,9 @@
// Support for pins which are on TIM1_CH1N
#ifdef BACKLIGHT_PWM_COMPLEMENTARY_OUTPUT
# if BACKLIGHT_ON_STATE == 1
-# define PWM_OUTPUT_MODE PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW;
-# else
# define PWM_OUTPUT_MODE PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH;
+# else
+# define PWM_OUTPUT_MODE PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW;
# endif
#else
# if BACKLIGHT_ON_STATE == 1
diff --git a/platforms/chibios/drivers/eeprom/eeprom_stm32_L0_L1.c b/platforms/chibios/drivers/eeprom/eeprom_stm32_L0_L1.c
index 628137a0b3..31062a4816 100644
--- a/platforms/chibios/drivers/eeprom/eeprom_stm32_L0_L1.c
+++ b/platforms/chibios/drivers/eeprom/eeprom_stm32_L0_L1.c
@@ -25,6 +25,7 @@
#define EEPROM_ADDR(offset) (EEPROM_BASE_ADDR + (offset))
#define EEPROM_PTR(offset) ((__IO uint8_t *)EEPROM_ADDR(offset))
#define EEPROM_BYTE(location, offset) (*(EEPROM_PTR(((uint32_t)location) + ((uint32_t)offset))))
+#define EEPROM_WORD(location) (*(__IO uint32_t *)EEPROM_PTR(location))
#define BUFFER_BYTE(buffer, offset) (*(((uint8_t *)buffer) + offset))
@@ -62,12 +63,16 @@ void eeprom_driver_erase(void) {
STM32_L0_L1_EEPROM_Unlock();
for (size_t offset = 0; offset < STM32_ONBOARD_EEPROM_SIZE; offset += sizeof(uint32_t)) {
+#ifdef QMK_MCU_SERIES_STM32L0XX
FLASH->PECR |= FLASH_PECR_ERASE | FLASH_PECR_DATA;
+#endif
- *(__IO uint32_t *)EEPROM_ADDR(offset) = (uint32_t)0;
+ EEPROM_WORD(offset) = (uint32_t)0;
STM32_L0_L1_EEPROM_WaitNotBusy();
+#ifdef QMK_MCU_SERIES_STM32L0XX
FLASH->PECR &= ~(FLASH_PECR_ERASE | FLASH_PECR_DATA);
+#endif
}
STM32_L0_L1_EEPROM_Lock();
@@ -86,17 +91,39 @@ void eeprom_read_block(void *buf, const void *addr, size_t len) {
}
void eeprom_write_block(const void *buf, void *addr, size_t len) {
- STM32_L0_L1_EEPROM_Unlock();
+ // use word-aligned write to overcome issues with writing null bytes
+ uint32_t start_addr = (uint32_t)addr;
+ if (start_addr >= (STM32_ONBOARD_EEPROM_SIZE)) {
+ return;
+ }
+ uint32_t max_len = (STM32_ONBOARD_EEPROM_SIZE)-start_addr;
+ if (len > max_len) {
+ len = max_len;
+ }
+ uint32_t end_addr = start_addr + len;
- for (size_t offset = 0; offset < len; ++offset) {
- // Drop out if we've hit the limit of the EEPROM
- if ((((uint32_t)addr) + offset) >= STM32_ONBOARD_EEPROM_SIZE) {
- break;
+ uint32_t aligned_start = start_addr & ~0x3;
+ uint32_t aligned_end = (end_addr + 3) & ~0x3;
+
+ STM32_L0_L1_EEPROM_Unlock();
+ for (uint32_t word_addr = aligned_start; word_addr < aligned_end; word_addr += 4) {
+ uint32_t existing_word = EEPROM_WORD(word_addr);
+ uint32_t new_word = existing_word;
+
+ // Update the relevant bytes in the word
+ for (int i = 0; i < 4; i++) {
+ uint32_t byte_addr = word_addr + i;
+ if (byte_addr >= start_addr && byte_addr < end_addr) {
+ uint8_t new_byte = BUFFER_BYTE(buf, byte_addr - start_addr);
+ new_word = (new_word & ~(0xFFU << (i * 8))) | ((uint32_t)new_byte << (i * 8));
+ }
}
- STM32_L0_L1_EEPROM_WaitNotBusy();
- EEPROM_BYTE(addr, offset) = BUFFER_BYTE(buf, offset);
+ // Only write if the word has changed
+ if (new_word != existing_word) {
+ STM32_L0_L1_EEPROM_WaitNotBusy();
+ EEPROM_WORD(word_addr) = new_word;
+ }
}
-
STM32_L0_L1_EEPROM_Lock();
}
diff --git a/platforms/chibios/drivers/i2c_master.c b/platforms/chibios/drivers/i2c_master.c
index 0d5fb1e985..20850859b5 100644
--- a/platforms/chibios/drivers/i2c_master.c
+++ b/platforms/chibios/drivers/i2c_master.c
@@ -29,17 +29,37 @@
#include "i2c_master.h"
#include "gpio.h"
#include "chibios_config.h"
-#include <string.h>
#include <ch.h>
#include <hal.h>
+#ifndef I2C_DRIVER
+# define I2C_DRIVER I2CD1
+#endif
+
#ifndef I2C1_SCL_PIN
# define I2C1_SCL_PIN B6
#endif
+
+#ifndef I2C1_SCL_PAL_MODE
+# ifdef USE_GPIOV1
+# define I2C1_SCL_PAL_MODE PAL_MODE_ALTERNATE_OPENDRAIN
+# else
+# define I2C1_SCL_PAL_MODE 4
+# endif
+#endif
+
#ifndef I2C1_SDA_PIN
# define I2C1_SDA_PIN B7
#endif
+#ifndef I2C1_SDA_PAL_MODE
+# ifdef USE_GPIOV1
+# define I2C1_SDA_PAL_MODE PAL_MODE_ALTERNATE_OPENDRAIN
+# else
+# define I2C1_SDA_PAL_MODE 4
+# endif
+#endif
+
#ifdef USE_I2CV1
# ifndef I2C1_OPMODE
# define I2C1_OPMODE OPMODE_I2C
@@ -70,27 +90,6 @@
# endif
#endif
-#ifndef I2C_DRIVER
-# define I2C_DRIVER I2CD1
-#endif
-
-#ifdef USE_GPIOV1
-# ifndef I2C1_SCL_PAL_MODE
-# define I2C1_SCL_PAL_MODE PAL_MODE_ALTERNATE_OPENDRAIN
-# endif
-# ifndef I2C1_SDA_PAL_MODE
-# define I2C1_SDA_PAL_MODE PAL_MODE_ALTERNATE_OPENDRAIN
-# endif
-#else
-// The default PAL alternate modes are used to signal that the pins are used for I2C
-# ifndef I2C1_SCL_PAL_MODE
-# define I2C1_SCL_PAL_MODE 4
-# endif
-# ifndef I2C1_SDA_PAL_MODE
-# define I2C1_SDA_PAL_MODE 4
-# endif
-#endif
-
static const I2CConfig i2cconfig = {
#if defined(USE_I2CV1_CONTRIB)
I2C1_CLOCK_SPEED,
@@ -207,4 +206,4 @@ __attribute__((weak)) i2c_status_t i2c_ping_address(uint8_t address, uint16_t ti
// This approach may produce false negative results for I2C devices that do not respond to a register 0 read request.
uint8_t data = 0;
return i2c_read_register(address, 0, &data, sizeof(data), timeout);
-} \ No newline at end of file
+}
diff --git a/platforms/chibios/drivers/i2c_master.h b/platforms/chibios/drivers/i2c_master.h
deleted file mode 100644
index 132ffd14c0..0000000000
--- a/platforms/chibios/drivers/i2c_master.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* Copyright 2018 Jack Humbert
- * Copyright 2018 Yiancar
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-/* This library follows the convention of the AVR i2c_master library.
- * As a result addresses are expected to be already shifted (addr << 1).
- * I2CD1 is the default driver which corresponds to pins B6 and B7. This
- * can be changed.
- * Please ensure that HAL_USE_I2C is TRUE in the halconf.h file and that
- * STM32_I2C_USE_I2C1 is TRUE in the mcuconf.h file.
- */
-#pragma once
-
-#include <stdint.h>
-
-// ### DEPRECATED - DO NOT USE ###
-#define i2c_writeReg(devaddr, regaddr, data, length, timeout) i2c_write_register(devaddr, regaddr, data, length, timeout)
-#define i2c_writeReg16(devaddr, regaddr, data, length, timeout) i2c_write_register16(devaddr, regaddr, data, length, timeout)
-#define i2c_readReg(devaddr, regaddr, data, length, timeout) i2c_read_register(devaddr, regaddr, data, length, timeout)
-#define i2c_readReg16(devaddr, regaddr, data, length, timeout) i2c_read_register16(devaddr, regaddr, data, length, timeout)
-// ###############################
-
-typedef int16_t i2c_status_t;
-
-#define I2C_STATUS_SUCCESS (0)
-#define I2C_STATUS_ERROR (-1)
-#define I2C_STATUS_TIMEOUT (-2)
-
-void i2c_init(void);
-i2c_status_t i2c_transmit(uint8_t address, const uint8_t* data, uint16_t length, uint16_t timeout);
-i2c_status_t i2c_receive(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout);
-i2c_status_t i2c_write_register(uint8_t devaddr, uint8_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout);
-i2c_status_t i2c_write_register16(uint8_t devaddr, uint16_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout);
-i2c_status_t i2c_read_register(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout);
-i2c_status_t i2c_read_register16(uint8_t devaddr, uint16_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout);
-i2c_status_t i2c_ping_address(uint8_t address, uint16_t timeout);
diff --git a/platforms/chibios/drivers/spi_master.c b/platforms/chibios/drivers/spi_master.c
index 414e5b10a3..f5e48edfda 100644
--- a/platforms/chibios/drivers/spi_master.c
+++ b/platforms/chibios/drivers/spi_master.c
@@ -15,8 +15,49 @@
*/
#include "spi_master.h"
+#include "chibios_config.h"
+#include <ch.h>
+#include <hal.h>
-#include "timer.h"
+#ifndef SPI_DRIVER
+# define SPI_DRIVER SPID2
+#endif
+
+#ifndef SPI_SCK_PIN
+# define SPI_SCK_PIN B13
+#endif
+
+#ifndef SPI_SCK_PAL_MODE
+# ifdef USE_GPIOV1
+# define SPI_SCK_PAL_MODE PAL_MODE_ALTERNATE_PUSHPULL
+# else
+# define SPI_SCK_PAL_MODE 5
+# endif
+#endif
+
+#ifndef SPI_MOSI_PIN
+# define SPI_MOSI_PIN B15
+#endif
+
+#ifndef SPI_MOSI_PAL_MODE
+# ifdef USE_GPIOV1
+# define SPI_MOSI_PAL_MODE PAL_MODE_ALTERNATE_PUSHPULL
+# else
+# define SPI_MOSI_PAL_MODE 5
+# endif
+#endif
+
+#ifndef SPI_MISO_PIN
+# define SPI_MISO_PIN B14
+#endif
+
+#ifndef SPI_MISO_PAL_MODE
+# ifdef USE_GPIOV1
+# define SPI_MISO_PAL_MODE PAL_MODE_ALTERNATE_PUSHPULL
+# else
+# define SPI_MISO_PAL_MODE 5
+# endif
+#endif
static bool spiStarted = false;
#if SPI_SELECT_MODE == SPI_SELECT_MODE_NONE
diff --git a/platforms/chibios/drivers/spi_master.h b/platforms/chibios/drivers/spi_master.h
deleted file mode 100644
index 4ad6144091..0000000000
--- a/platforms/chibios/drivers/spi_master.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* Copyright 2020 Nick Brassel (tzarc)
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <https://www.gnu.org/licenses/>.
- */
-
-#pragma once
-
-#include <ch.h>
-#include <hal.h>
-#include <stdbool.h>
-
-#include "gpio.h"
-#include "chibios_config.h"
-
-#ifndef SPI_DRIVER
-# define SPI_DRIVER SPID2
-#endif
-
-#ifndef SPI_SCK_PIN
-# define SPI_SCK_PIN B13
-#endif
-
-#ifndef SPI_SCK_PAL_MODE
-# if defined(USE_GPIOV1)
-# define SPI_SCK_PAL_MODE PAL_MODE_ALTERNATE_PUSHPULL
-# else
-# define SPI_SCK_PAL_MODE 5
-# endif
-#endif
-
-#ifndef SPI_MOSI_PIN
-# define SPI_MOSI_PIN B15
-#endif
-
-#ifndef SPI_MOSI_PAL_MODE
-# if defined(USE_GPIOV1)
-# define SPI_MOSI_PAL_MODE PAL_MODE_ALTERNATE_PUSHPULL
-# else
-# define SPI_MOSI_PAL_MODE 5
-# endif
-#endif
-
-#ifndef SPI_MISO_PIN
-# define SPI_MISO_PIN B14
-#endif
-
-#ifndef SPI_MISO_PAL_MODE
-# if defined(USE_GPIOV1)
-# define SPI_MISO_PAL_MODE PAL_MODE_ALTERNATE_PUSHPULL
-# else
-# define SPI_MISO_PAL_MODE 5
-# endif
-#endif
-
-typedef int16_t spi_status_t;
-
-#define SPI_STATUS_SUCCESS (0)
-#define SPI_STATUS_ERROR (-1)
-#define SPI_STATUS_TIMEOUT (-2)
-
-#define SPI_TIMEOUT_IMMEDIATE (0)
-#define SPI_TIMEOUT_INFINITE (0xFFFF)
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-typedef struct spi_start_config_t {
- pin_t slave_pin;
- bool lsb_first;
- uint8_t mode;
- uint16_t divisor;
- bool cs_active_low;
-} spi_start_config_t;
-
-void spi_init(void);
-
-bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor);
-bool spi_start_extended(spi_start_config_t *start_config);
-
-spi_status_t spi_write(uint8_t data);
-
-spi_status_t spi_read(void);
-
-spi_status_t spi_transmit(const uint8_t *data, uint16_t length);
-
-spi_status_t spi_receive(uint8_t *data, uint16_t length);
-
-void spi_stop(void);
-#ifdef __cplusplus
-}
-#endif
diff --git a/platforms/chibios/drivers/uart.h b/platforms/chibios/drivers/uart.h
deleted file mode 100644
index c1945575f1..0000000000
--- a/platforms/chibios/drivers/uart.h
+++ /dev/null
@@ -1,200 +0,0 @@
-// Copyright 2024 Stefan Kerkmann
-// Copyright 2021 QMK
-// Copyright 2024 Stefan Kerkmann
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#pragma once
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#include <hal.h>
-
-#include "gpio.h"
-#include "chibios_config.h"
-
-// ======== DEPRECATED DEFINES - DO NOT USE ========
-#ifdef SERIAL_DRIVER
-# define UART_DRIVER SERIAL_DRIVER
-#endif
-#ifdef SD1_TX_PIN
-# define UART_TX_PIN SD1_TX_PIN
-#endif
-#ifdef SD1_RX_PIN
-# define UART_RX_PIN SD1_RX_PIN
-#endif
-#ifdef SD1_CTS_PIN
-# define UART_CTS_PIN SD1_CTS_PIN
-#endif
-#ifdef SD1_RTS_PIN
-# define UART_RTS_PIN SD1_RTS_PIN
-#endif
-#ifdef SD1_TX_PAL_MODE
-# define UART_TX_PAL_MODE SD1_TX_PAL_MODE
-#endif
-#ifdef SD1_RX_PAL_MODE
-# define UART_RX_PAL_MODE SD1_RX_PAL_MODE
-#endif
-#ifdef SD1_CTS_PAL_MODE
-# define UART_RTS_PAL_MODE SD1_CTS_PAL_MODE
-#endif
-#ifdef SD1_RTS_PAL_MODE
-# define UART_TX_PAL_MODE SD1_RTS_PAL_MODE
-#endif
-#ifdef SD1_CR1
-# define UART_CR1 SD1_CR1
-#endif
-#ifdef SD1_CR2
-# define UART_CR2 SD1_CR2
-#endif
-#ifdef SD1_CR3
-# define UART_CR3 SD1_CR3
-#endif
-#ifdef SD1_WRDLEN
-# define UART_WRDLEN SD1_WRDLEN
-#endif
-#ifdef SD1_STPBIT
-# define UART_STPBIT SD1_STPBIT
-#endif
-#ifdef SD1_PARITY
-# define UART_PARITY SD1_PARITY
-#endif
-#ifdef SD1_ATFLCT
-# define UART_ATFLCT SD1_ATFLCT
-#endif
-// ========
-
-#ifndef UART_DRIVER
-# if (HAL_USE_SERIAL == TRUE)
-# define UART_DRIVER SD1
-# elif (HAL_USE_SIO == TRUE)
-# define UART_DRIVER SIOD1
-# endif
-#endif
-
-#ifndef UART_TX_PIN
-# define UART_TX_PIN A9
-#endif
-
-#ifndef UART_RX_PIN
-# define UART_RX_PIN A10
-#endif
-
-#ifndef UART_CTS_PIN
-# define UART_CTS_PIN A11
-#endif
-
-#ifndef UART_RTS_PIN
-# define UART_RTS_PIN A12
-#endif
-
-#ifdef USE_GPIOV1
-# ifndef UART_TX_PAL_MODE
-# define UART_TX_PAL_MODE PAL_MODE_ALTERNATE_PUSHPULL
-# endif
-# ifndef UART_RX_PAL_MODE
-# define UART_RX_PAL_MODE PAL_MODE_INPUT
-# endif
-# ifndef UART_CTS_PAL_MODE
-# define UART_CTS_PAL_MODE PAL_MODE_INPUT
-# endif
-# ifndef UART_RTS_PAL_MODE
-# define UART_RTS_PAL_MODE PAL_MODE_ALTERNATE_PUSHPULL
-# endif
-#else
-# ifndef UART_TX_PAL_MODE
-# define UART_TX_PAL_MODE 7
-# endif
-
-# ifndef UART_RX_PAL_MODE
-# define UART_RX_PAL_MODE 7
-# endif
-
-# ifndef UART_CTS_PAL_MODE
-# define UART_CTS_PAL_MODE 7
-# endif
-
-# ifndef UART_RTS_PAL_MODE
-# define UART_RTS_PAL_MODE 7
-# endif
-#endif
-
-#ifndef UART_CR1
-# define UART_CR1 0
-#endif
-
-#ifndef UART_CR2
-# define UART_CR2 0
-#endif
-
-#ifndef UART_CR3
-# define UART_CR3 0
-#endif
-
-#ifndef UART_WRDLEN
-# define UART_WRDLEN 3
-#endif
-
-#ifndef UART_STPBIT
-# define UART_STPBIT 0
-#endif
-
-#ifndef UART_PARITY
-# define UART_PARITY 0
-#endif
-
-#ifndef UART_ATFLCT
-# define UART_ATFLCT 0
-#endif
-
-/**
- * @brief Initialize the UART driver. This function must be called only once,
- * before any of the below functions can be called.
- *
- * @param baud The baud rate to transmit and receive at. This may depend on the
- * device you are communicating with. Common values are 1200, 2400, 4800, 9600,
- * 19200, 38400, 57600, and 115200.
- */
-void uart_init(uint32_t baud);
-
-/**
- * @brief Transmit a single byte.
- *
- * @param data The byte to transmit.
- */
-void uart_write(uint8_t data);
-
-/**
- * @brief Receive a single byte.
- *
- * @return uint8_t The byte read from the receive buffer. This function will
- * block if the buffer is empty (ie. no data to read).
- */
-uint8_t uart_read(void);
-
-/**
- * @brief Transmit multiple bytes.
- *
- * @param data A pointer to the data to write from.
- * @param length The number of bytes to write. Take care not to overrun the
- * length of `data`.
- */
-void uart_transmit(const uint8_t *data, uint16_t length);
-
-/**
- * @brief Receive multiple bytes.
- *
- * @param data A pointer to the buffer to read into.
- * @param length The number of bytes to read. Take care not to overrun the
- * length of `data`.
- */
-void uart_receive(uint8_t *data, uint16_t length);
-
-/**
- * @brief Return whether the receive buffer contains data. Call this function
- * to determine if `uart_read()` will return data immediately.
- *
- * @return true If there is data available to read.
- * @return false If there is no data available to read.
- */
-bool uart_available(void);
diff --git a/platforms/chibios/drivers/uart_serial.c b/platforms/chibios/drivers/uart_serial.c
index 6aff4eae47..e0afb9768a 100644
--- a/platforms/chibios/drivers/uart_serial.c
+++ b/platforms/chibios/drivers/uart_serial.c
@@ -3,6 +3,89 @@
// SPDX-License-Identifier: GPL-2.0-or-later
#include "uart.h"
+#include "gpio.h"
+#include "chibios_config.h"
+#include <hal.h>
+
+#ifndef UART_DRIVER
+# define UART_DRIVER SD1
+#endif
+
+#ifndef UART_TX_PIN
+# define UART_TX_PIN A9
+#endif
+
+#ifndef UART_TX_PAL_MODE
+# ifdef USE_GPIOV1
+# define UART_TX_PAL_MODE PAL_MODE_ALTERNATE_PUSHPULL
+# else
+# define UART_TX_PAL_MODE 7
+# endif
+#endif
+
+#ifndef UART_RX_PIN
+# define UART_RX_PIN A10
+#endif
+
+#ifndef UART_RX_PAL_MODE
+# ifdef USE_GPIOV1
+# define UART_RX_PAL_MODE PAL_MODE_INPUT
+# else
+# define UART_RX_PAL_MODE 7
+# endif
+#endif
+
+#ifndef UART_CTS_PIN
+# define UART_CTS_PIN A11
+#endif
+
+#ifndef UART_CTS_PAL_MODE
+# ifdef USE_GPIOV1
+# define UART_CTS_PAL_MODE PAL_MODE_INPUT
+# else
+# define UART_CTS_PAL_MODE 7
+# endif
+#endif
+
+#ifndef UART_RTS_PIN
+# define UART_RTS_PIN A12
+#endif
+
+#ifndef UART_RTS_PAL_MODE
+# ifdef USE_GPIOV1
+# define UART_RTS_PAL_MODE PAL_MODE_ALTERNATE_PUSHPULL
+# else
+# define UART_RTS_PAL_MODE 7
+# endif
+#endif
+
+#ifndef UART_CR1
+# define UART_CR1 0
+#endif
+
+#ifndef UART_CR2
+# define UART_CR2 0
+#endif
+
+#ifndef UART_CR3
+# define UART_CR3 0
+#endif
+
+#ifndef UART_WRDLEN
+# define UART_WRDLEN 3
+#endif
+
+#ifndef UART_STPBIT
+# define UART_STPBIT 0
+#endif
+
+#ifndef UART_PARITY
+# define UART_PARITY 0
+#endif
+
+#ifndef UART_ATFLCT
+# define UART_ATFLCT 0
+#endif
#if defined(MCU_KINETIS)
static SerialConfig serialConfig = {SERIAL_DEFAULT_BITRATE};
diff --git a/platforms/chibios/drivers/uart_sio.c b/platforms/chibios/drivers/uart_sio.c
index 442df1c54d..fc12f0abed 100644
--- a/platforms/chibios/drivers/uart_sio.c
+++ b/platforms/chibios/drivers/uart_sio.c
@@ -3,6 +3,73 @@
// SPDX-License-Identifier: GPL-2.0-or-later
#include "uart.h"
+#include "gpio.h"
+#include "chibios_config.h"
+#include <hal.h>
+
+#ifndef UART_DRIVER
+# define UART_DRIVER SIOD1
+#endif
+
+#ifndef UART_TX_PIN
+# define UART_TX_PIN A9
+#endif
+
+#ifndef UART_TX_PAL_MODE
+# ifdef USE_GPIOV1
+# define UART_TX_PAL_MODE PAL_MODE_ALTERNATE_PUSHPULL
+# else
+# define UART_TX_PAL_MODE 7
+# endif
+#endif
+
+#ifndef UART_RX_PIN
+# define UART_RX_PIN A10
+#endif
+
+#ifndef UART_RX_PAL_MODE
+# ifdef USE_GPIOV1
+# define UART_RX_PAL_MODE PAL_MODE_INPUT
+# else
+# define UART_RX_PAL_MODE 7
+# endif
+#endif
+
+#ifndef UART_CTS_PIN
+# define UART_CTS_PIN A11
+#endif
+
+#ifndef UART_CTS_PAL_MODE
+# ifdef USE_GPIOV1
+# define UART_CTS_PAL_MODE PAL_MODE_INPUT
+# else
+# define UART_CTS_PAL_MODE 7
+# endif
+#endif
+
+#ifndef UART_RTS_PIN
+# define UART_RTS_PIN A12
+#endif
+
+#ifndef UART_RTS_PAL_MODE
+# ifdef USE_GPIOV1
+# define UART_RTS_PAL_MODE PAL_MODE_ALTERNATE_PUSHPULL
+# else
+# define UART_RTS_PAL_MODE 7
+# endif
+#endif
+
+#ifndef UART_CR1
+# define UART_CR1 0
+#endif
+
+#ifndef UART_CR2
+# define UART_CR2 0
+#endif
+
+#ifndef UART_CR3
+# define UART_CR3 0
+#endif
#if defined(MCU_RP)
// 38400 baud, 8 data bits, 1 stop bit, no parity, no flow control
diff --git a/platforms/chibios/drivers/usbpd_stm32g4.c b/platforms/chibios/drivers/usbpd_stm32g4.c
index 21b8f6db95..7603b5627b 100644
--- a/platforms/chibios/drivers/usbpd_stm32g4.c
+++ b/platforms/chibios/drivers/usbpd_stm32g4.c
@@ -76,4 +76,4 @@ __attribute__((weak)) usbpd_allowance_t usbpd_get_allowance(void) {
}
return USBPD_500MA;
-} \ No newline at end of file
+}
diff --git a/platforms/chibios/drivers/wear_leveling/wear_leveling_efl.c b/platforms/chibios/drivers/wear_leveling/wear_leveling_efl.c
index fed16d20b1..fec4646a5b 100644
--- a/platforms/chibios/drivers/wear_leveling/wear_leveling_efl.c
+++ b/platforms/chibios/drivers/wear_leveling/wear_leveling_efl.c
@@ -4,6 +4,7 @@
#include <hal.h>
#include "timer.h"
#include "wear_leveling.h"
+#include "wear_leveling_efl_config.h"
#include "wear_leveling_internal.h"
static flash_offset_t base_offset = UINT32_MAX;
diff --git a/platforms/chibios/drivers/wear_leveling/wear_leveling_legacy.c b/platforms/chibios/drivers/wear_leveling/wear_leveling_legacy.c
index 7c6fd2d808..3d2af625ca 100644
--- a/platforms/chibios/drivers/wear_leveling/wear_leveling_legacy.c
+++ b/platforms/chibios/drivers/wear_leveling/wear_leveling_legacy.c
@@ -4,6 +4,7 @@
#include <hal.h>
#include "timer.h"
#include "wear_leveling.h"
+#include "wear_leveling_legacy_config.h"
#include "wear_leveling_internal.h"
#include "legacy_flash_ops.h"
diff --git a/platforms/chibios/drivers/wear_leveling/wear_leveling_rp2040_flash.c b/platforms/chibios/drivers/wear_leveling/wear_leveling_rp2040_flash.c
index 6624c30b5b..2f3c7c58ca 100644
--- a/platforms/chibios/drivers/wear_leveling/wear_leveling_rp2040_flash.c
+++ b/platforms/chibios/drivers/wear_leveling/wear_leveling_rp2040_flash.c
@@ -6,15 +6,18 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <stdbool.h>
+
#include "pico/bootrom.h"
#include "hardware/flash.h"
#include "hardware/sync.h"
#include "hardware/structs/ssi.h"
#include "hardware/structs/ioqspi.h"
-#include <stdbool.h>
+#include "compiler_support.h"
#include "timer.h"
#include "wear_leveling.h"
+#include "wear_leveling_rp2040_flash_config.h"
#include "wear_leveling_internal.h"
#ifndef WEAR_LEVELING_RP2040_FLASH_BULK_COUNT
@@ -177,7 +180,7 @@ bool backing_store_erase(void) {
#endif
// Ensure the backing size can be cleanly subtracted from the flash size without alignment issues.
- _Static_assert((WEAR_LEVELING_BACKING_SIZE) % (FLASH_SECTOR_SIZE) == 0, "Backing size must be a multiple of FLASH_SECTOR_SIZE");
+ STATIC_ASSERT((WEAR_LEVELING_BACKING_SIZE) % (FLASH_SECTOR_SIZE) == 0, "Backing size must be a multiple of FLASH_SECTOR_SIZE");
interrupts = save_and_disable_interrupts();
flash_range_erase((WEAR_LEVELING_RP2040_FLASH_BASE), (WEAR_LEVELING_BACKING_SIZE));
diff --git a/platforms/chibios/errno.h b/platforms/chibios/errno.h
new file mode 100644
index 0000000000..a411ed9821
--- /dev/null
+++ b/platforms/chibios/errno.h
@@ -0,0 +1,13 @@
+// Copyright 2025 Nick Brassel (@tzarc)
+// SPDX-License-Identifier: GPL-2.0-or-later
+#pragma once
+#include_next <errno.h>
+
+// Newer versions of picolibc don't seem to provide `__errno_r(r)` in the header file, but is used by ChibiOS.
+#ifndef __errno_r
+# ifdef __REENT_ERRNO
+# define __errno_r(r) _REENT_ERRNO(r)
+# else
+# define __errno_r(r) (errno)
+# endif
+#endif
diff --git a/platforms/chibios/mcu_selection.mk b/platforms/chibios/mcu_selection.mk
index 086a2b31c6..199bdb2321 100644
--- a/platforms/chibios/mcu_selection.mk
+++ b/platforms/chibios/mcu_selection.mk
@@ -511,6 +511,41 @@ ifneq ($(findstring STM32F446, $(MCU)),)
EEPROM_DRIVER ?= transient
endif
+ifneq ($(findstring STM32G0B1, $(MCU)),)
+ # Cortex version
+ MCU = cortex-m0plus
+
+ # ARM version, CORTEX-M0/M1 are 6, CORTEX-M3/M4/M7 are 7
+ ARMV = 6
+
+ ## chip/board settings
+ # - the next two should match the directories in
+ # <chibios[-contrib]>/os/hal/ports/$(MCU_PORT_NAME)/$(MCU_SERIES)
+ # OR
+ # <chibios[-contrib]>/os/hal/ports/$(MCU_FAMILY)/$(MCU_SERIES)
+ MCU_FAMILY = STM32
+ MCU_SERIES = STM32G0xx
+
+ # Linker script to use
+ # - it should exist either in <chibios>/os/common/startup/ARMCMx/compilers/GCC/ld/
+ # or <keyboard_dir>/ld/
+ MCU_LDSCRIPT ?= STM32G0B1xB
+
+ # Startup code to use
+ # - it should exist in <chibios>/os/common/startup/ARMCMx/compilers/GCC/mk/
+ MCU_STARTUP ?= stm32g0xx
+
+ # Board: it should exist either in <chibios>/os/hal/boards/,
+ # <keyboard_dir>/boards/, or drivers/boards/
+ BOARD ?= GENERIC_STM32_G0B1XB
+
+ # UF2 settings
+ UF2_FAMILY ?= STM32G0
+
+ # Bootloader address for STM32 DFU
+ STM32_BOOTLOADER_ADDRESS ?= 0x1FFF0000
+endif
+
ifneq ($(findstring STM32G431, $(MCU)),)
# Cortex version
MCU = cortex-m4
diff --git a/platforms/chibios/platform.c b/platforms/chibios/platform.c
index d4a229f278..e559f178cd 100644
--- a/platforms/chibios/platform.c
+++ b/platforms/chibios/platform.c
@@ -19,4 +19,4 @@
void platform_setup(void) {
halInit();
chSysInit();
-} \ No newline at end of file
+}
diff --git a/platforms/chibios/timer.c b/platforms/chibios/timer.c
index 4a347b445d..9f7eade83f 100644
--- a/platforms/chibios/timer.c
+++ b/platforms/chibios/timer.c
@@ -99,7 +99,7 @@ uint16_t timer_read(void) {
}
uint32_t timer_read32(void) {
- chSysLock();
+ syssts_t sts = chSysGetStatusAndLockX();
uint32_t ticks = get_system_time_ticks() - ticks_offset;
if (ticks < last_ticks) {
// The 32-bit tick counter overflowed and wrapped around. We cannot just extend the counter to 64 bits here,
@@ -114,15 +114,7 @@ uint32_t timer_read32(void) {
}
last_ticks = ticks;
uint32_t ms_offset_copy = ms_offset; // read while still holding the lock to ensure a consistent value
- chSysUnlock();
+ chSysRestoreStatusX(sts);
return (uint32_t)TIME_I2MS(ticks) + ms_offset_copy;
}
-
-uint16_t timer_elapsed(uint16_t last) {
- return TIMER_DIFF_16(timer_read(), last);
-}
-
-uint32_t timer_elapsed32(uint32_t last) {
- return TIMER_DIFF_32(timer_read32(), last);
-}
diff --git a/platforms/chibios/vendors/RP/RP2040.mk b/platforms/chibios/vendors/RP/RP2040.mk
index 94f023d72b..27d1fa4472 100644
--- a/platforms/chibios/vendors/RP/RP2040.mk
+++ b/platforms/chibios/vendors/RP/RP2040.mk
@@ -78,7 +78,7 @@ PICOSDKINTRINSICSSRC = $(PICOSDKROOT)/src/rp2_common/pico_divider/divider.S \
$(PICOSDKROOT)/src/rp2_common/pico_int64_ops/pico_int64_ops_aeabi.S
PICOSDKINTRINSICSINC = $(PICOSDKROOT)/src/common/pico_base/include \
- $(PICOSDKROOT)/src/rp2_common/pico_platfrom/include \
+ $(PICOSDKROOT)/src/rp2_common/pico_platform/include \
$(PICOSDKROOT)/src/rp2_common/hardware_divider/include
# integer division intrinsics utilizing the RP2040 hardware divider