diff options
Diffstat (limited to 'platforms/chibios/drivers')
-rw-r--r-- | platforms/chibios/drivers/analog.c | 23 | ||||
-rw-r--r-- | platforms/chibios/drivers/audio_pwm_hardware.c | 18 | ||||
-rw-r--r-- | platforms/chibios/drivers/backlight_pwm.c | 4 | ||||
-rw-r--r-- | platforms/chibios/drivers/eeprom/eeprom_stm32_L0_L1.c | 45 | ||||
-rw-r--r-- | platforms/chibios/drivers/i2c_master.c | 45 | ||||
-rw-r--r-- | platforms/chibios/drivers/i2c_master.h | 49 | ||||
-rw-r--r-- | platforms/chibios/drivers/spi_master.c | 43 | ||||
-rw-r--r-- | platforms/chibios/drivers/spi_master.h | 102 | ||||
-rw-r--r-- | platforms/chibios/drivers/uart.h | 200 | ||||
-rw-r--r-- | platforms/chibios/drivers/uart_serial.c | 83 | ||||
-rw-r--r-- | platforms/chibios/drivers/uart_sio.c | 67 | ||||
-rw-r--r-- | platforms/chibios/drivers/usbpd_stm32g4.c | 2 | ||||
-rw-r--r-- | platforms/chibios/drivers/wear_leveling/wear_leveling_efl.c | 1 | ||||
-rw-r--r-- | platforms/chibios/drivers/wear_leveling/wear_leveling_legacy.c | 1 | ||||
-rw-r--r-- | platforms/chibios/drivers/wear_leveling/wear_leveling_rp2040_flash.c | 7 |
15 files changed, 292 insertions, 398 deletions
diff --git a/platforms/chibios/drivers/analog.c b/platforms/chibios/drivers/analog.c index 7e1f87e6c9..a916cc9a1d 100644 --- a/platforms/chibios/drivers/analog.c +++ b/platforms/chibios/drivers/analog.c @@ -43,7 +43,7 @@ #endif // Otherwise assume V3 -#if defined(STM32F0XX) || defined(STM32L0XX) +#if defined(STM32F0XX) || defined(STM32L0XX) || defined(STM32G0XX) # define USE_ADCV1 #elif defined(STM32F1XX) || defined(STM32F2XX) || defined(STM32F4XX) || defined(GD32VF103) || defined(WB32F3G71xx) || defined(WB32FQ95xx) || defined(AT32F415) # define USE_ADCV2 @@ -82,7 +82,7 @@ /* User configurable ADC options */ #ifndef ADC_COUNT -# if defined(RP2040) || defined(STM32F0XX) || defined(STM32F1XX) || defined(STM32F4XX) || defined(GD32VF103) || defined(WB32F3G71xx) || defined(WB32FQ95xx) || defined(AT32F415) +# if defined(RP2040) || defined(STM32F0XX) || defined(STM32F1XX) || defined(STM32F4XX) || defined(STM32G0XX) || defined(GD32VF103) || defined(WB32F3G71xx) || defined(WB32FQ95xx) || defined(AT32F415) # define ADC_COUNT 1 # elif defined(STM32F3XX) || defined(STM32G4XX) # define ADC_COUNT 4 @@ -114,6 +114,8 @@ # define ADC_SAMPLING_RATE ADC_SMPR_SMP_1P5 # elif defined(ADC_SMPR_SMP_2P5) // STM32L4XX, STM32L4XXP, STM32G4XX, STM32WBXX # define ADC_SAMPLING_RATE ADC_SMPR_SMP_2P5 +# elif defined(ADC_SMPR_SMP1_1P5) // STM32G0XX +# define ADC_SAMPLING_RATE ADC_SMPR_SMP1_1P5 # else # error "Cannot determine the default ADC_SAMPLING_RATE for this MCU." # endif @@ -293,6 +295,23 @@ __attribute__((weak)) adc_mux pinToMux(pin_t pin) { case F9: return TO_MUX( ADC_CHANNEL_IN12, 2 ); case F10: return TO_MUX( ADC_CHANNEL_IN13, 2 ); # endif +#elif defined(STM32G0XX) + case A0: return TO_MUX( 0, 0 ); + case A1: return TO_MUX( 1, 0 ); + case A2: return TO_MUX( 2, 0 ); + case A3: return TO_MUX( 3, 0 ); + case A4: return TO_MUX( 4, 0 ); + case A5: return TO_MUX( 5, 0 ); + case A6: return TO_MUX( 6, 0 ); + case A7: return TO_MUX( 7, 0 ); + case B0: return TO_MUX( 8, 0 ); + case B1: return TO_MUX( 9, 0 ); + case B2: return TO_MUX( 10, 0 ); + case B10: return TO_MUX( 11, 0 ); + case B11: return TO_MUX( 15, 0 ); + case B12: return TO_MUX( 16, 0 ); + case C4: return TO_MUX( 17, 0 ); + case C5: return TO_MUX( 18, 0 ); #elif defined(STM32G4XX) case A0: return TO_MUX( ADC_CHANNEL_IN1, 0 ); // Can also be ADC2 case A1: return TO_MUX( ADC_CHANNEL_IN2, 0 ); // Can also be ADC2 diff --git a/platforms/chibios/drivers/audio_pwm_hardware.c b/platforms/chibios/drivers/audio_pwm_hardware.c index 1ba7ec13bc..afa341abb6 100644 --- a/platforms/chibios/drivers/audio_pwm_hardware.c +++ b/platforms/chibios/drivers/audio_pwm_hardware.c @@ -41,18 +41,19 @@ static float channel_1_frequency = 0.0f; void channel_1_set_frequency(float freq) { channel_1_frequency = freq; + pwmcnt_t period; + pwmcnt_t width; if (freq <= 0.0) { - // a pause/rest has freq=0 - return; + period = 2; + width = 0; + } else { + period = (pwmCFG.frequency / freq); + width = (pwmcnt_t)(((period) * (pwmcnt_t)((100 - note_timbre) * 100)) / (pwmcnt_t)(10000)); } - - pwmcnt_t period = (pwmCFG.frequency / freq); chSysLockFromISR(); pwmChangePeriodI(&AUDIO_PWM_DRIVER, period); - pwmEnableChannelI(&AUDIO_PWM_DRIVER, AUDIO_PWM_CHANNEL - 1, - // adjust the duty-cycle so that the output is for 'note_timbre' duration HIGH - PWM_PERCENTAGE_TO_WIDTH(&AUDIO_PWM_DRIVER, (100 - note_timbre) * 100)); + pwmEnableChannelI(&AUDIO_PWM_DRIVER, AUDIO_PWM_CHANNEL - 1, width); chSysUnlockFromISR(); } @@ -67,6 +68,9 @@ void channel_1_start(void) { void channel_1_stop(void) { pwmStop(&AUDIO_PWM_DRIVER); + pwmStart(&AUDIO_PWM_DRIVER, &pwmCFG); + pwmEnableChannel(&AUDIO_PWM_DRIVER, AUDIO_PWM_CHANNEL - 1, 0); + pwmStop(&AUDIO_PWM_DRIVER); } static virtual_timer_t audio_vt; diff --git a/platforms/chibios/drivers/backlight_pwm.c b/platforms/chibios/drivers/backlight_pwm.c index 25fe7962b0..47ad008415 100644 --- a/platforms/chibios/drivers/backlight_pwm.c +++ b/platforms/chibios/drivers/backlight_pwm.c @@ -28,9 +28,9 @@ // Support for pins which are on TIM1_CH1N #ifdef BACKLIGHT_PWM_COMPLEMENTARY_OUTPUT # if BACKLIGHT_ON_STATE == 1 -# define PWM_OUTPUT_MODE PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW; -# else # define PWM_OUTPUT_MODE PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH; +# else +# define PWM_OUTPUT_MODE PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW; # endif #else # if BACKLIGHT_ON_STATE == 1 diff --git a/platforms/chibios/drivers/eeprom/eeprom_stm32_L0_L1.c b/platforms/chibios/drivers/eeprom/eeprom_stm32_L0_L1.c index 628137a0b3..31062a4816 100644 --- a/platforms/chibios/drivers/eeprom/eeprom_stm32_L0_L1.c +++ b/platforms/chibios/drivers/eeprom/eeprom_stm32_L0_L1.c @@ -25,6 +25,7 @@ #define EEPROM_ADDR(offset) (EEPROM_BASE_ADDR + (offset)) #define EEPROM_PTR(offset) ((__IO uint8_t *)EEPROM_ADDR(offset)) #define EEPROM_BYTE(location, offset) (*(EEPROM_PTR(((uint32_t)location) + ((uint32_t)offset)))) +#define EEPROM_WORD(location) (*(__IO uint32_t *)EEPROM_PTR(location)) #define BUFFER_BYTE(buffer, offset) (*(((uint8_t *)buffer) + offset)) @@ -62,12 +63,16 @@ void eeprom_driver_erase(void) { STM32_L0_L1_EEPROM_Unlock(); for (size_t offset = 0; offset < STM32_ONBOARD_EEPROM_SIZE; offset += sizeof(uint32_t)) { +#ifdef QMK_MCU_SERIES_STM32L0XX FLASH->PECR |= FLASH_PECR_ERASE | FLASH_PECR_DATA; +#endif - *(__IO uint32_t *)EEPROM_ADDR(offset) = (uint32_t)0; + EEPROM_WORD(offset) = (uint32_t)0; STM32_L0_L1_EEPROM_WaitNotBusy(); +#ifdef QMK_MCU_SERIES_STM32L0XX FLASH->PECR &= ~(FLASH_PECR_ERASE | FLASH_PECR_DATA); +#endif } STM32_L0_L1_EEPROM_Lock(); @@ -86,17 +91,39 @@ void eeprom_read_block(void *buf, const void *addr, size_t len) { } void eeprom_write_block(const void *buf, void *addr, size_t len) { - STM32_L0_L1_EEPROM_Unlock(); + // use word-aligned write to overcome issues with writing null bytes + uint32_t start_addr = (uint32_t)addr; + if (start_addr >= (STM32_ONBOARD_EEPROM_SIZE)) { + return; + } + uint32_t max_len = (STM32_ONBOARD_EEPROM_SIZE)-start_addr; + if (len > max_len) { + len = max_len; + } + uint32_t end_addr = start_addr + len; - for (size_t offset = 0; offset < len; ++offset) { - // Drop out if we've hit the limit of the EEPROM - if ((((uint32_t)addr) + offset) >= STM32_ONBOARD_EEPROM_SIZE) { - break; + uint32_t aligned_start = start_addr & ~0x3; + uint32_t aligned_end = (end_addr + 3) & ~0x3; + + STM32_L0_L1_EEPROM_Unlock(); + for (uint32_t word_addr = aligned_start; word_addr < aligned_end; word_addr += 4) { + uint32_t existing_word = EEPROM_WORD(word_addr); + uint32_t new_word = existing_word; + + // Update the relevant bytes in the word + for (int i = 0; i < 4; i++) { + uint32_t byte_addr = word_addr + i; + if (byte_addr >= start_addr && byte_addr < end_addr) { + uint8_t new_byte = BUFFER_BYTE(buf, byte_addr - start_addr); + new_word = (new_word & ~(0xFFU << (i * 8))) | ((uint32_t)new_byte << (i * 8)); + } } - STM32_L0_L1_EEPROM_WaitNotBusy(); - EEPROM_BYTE(addr, offset) = BUFFER_BYTE(buf, offset); + // Only write if the word has changed + if (new_word != existing_word) { + STM32_L0_L1_EEPROM_WaitNotBusy(); + EEPROM_WORD(word_addr) = new_word; + } } - STM32_L0_L1_EEPROM_Lock(); } diff --git a/platforms/chibios/drivers/i2c_master.c b/platforms/chibios/drivers/i2c_master.c index 0d5fb1e985..20850859b5 100644 --- a/platforms/chibios/drivers/i2c_master.c +++ b/platforms/chibios/drivers/i2c_master.c @@ -29,17 +29,37 @@ #include "i2c_master.h" #include "gpio.h" #include "chibios_config.h" -#include <string.h> #include <ch.h> #include <hal.h> +#ifndef I2C_DRIVER +# define I2C_DRIVER I2CD1 +#endif + #ifndef I2C1_SCL_PIN # define I2C1_SCL_PIN B6 #endif + +#ifndef I2C1_SCL_PAL_MODE +# ifdef USE_GPIOV1 +# define I2C1_SCL_PAL_MODE PAL_MODE_ALTERNATE_OPENDRAIN +# else +# define I2C1_SCL_PAL_MODE 4 +# endif +#endif + #ifndef I2C1_SDA_PIN # define I2C1_SDA_PIN B7 #endif +#ifndef I2C1_SDA_PAL_MODE +# ifdef USE_GPIOV1 +# define I2C1_SDA_PAL_MODE PAL_MODE_ALTERNATE_OPENDRAIN +# else +# define I2C1_SDA_PAL_MODE 4 +# endif +#endif + #ifdef USE_I2CV1 # ifndef I2C1_OPMODE # define I2C1_OPMODE OPMODE_I2C @@ -70,27 +90,6 @@ # endif #endif -#ifndef I2C_DRIVER -# define I2C_DRIVER I2CD1 -#endif - -#ifdef USE_GPIOV1 -# ifndef I2C1_SCL_PAL_MODE -# define I2C1_SCL_PAL_MODE PAL_MODE_ALTERNATE_OPENDRAIN -# endif -# ifndef I2C1_SDA_PAL_MODE -# define I2C1_SDA_PAL_MODE PAL_MODE_ALTERNATE_OPENDRAIN -# endif -#else -// The default PAL alternate modes are used to signal that the pins are used for I2C -# ifndef I2C1_SCL_PAL_MODE -# define I2C1_SCL_PAL_MODE 4 -# endif -# ifndef I2C1_SDA_PAL_MODE -# define I2C1_SDA_PAL_MODE 4 -# endif -#endif - static const I2CConfig i2cconfig = { #if defined(USE_I2CV1_CONTRIB) I2C1_CLOCK_SPEED, @@ -207,4 +206,4 @@ __attribute__((weak)) i2c_status_t i2c_ping_address(uint8_t address, uint16_t ti // This approach may produce false negative results for I2C devices that do not respond to a register 0 read request. uint8_t data = 0; return i2c_read_register(address, 0, &data, sizeof(data), timeout); -}
\ No newline at end of file +} diff --git a/platforms/chibios/drivers/i2c_master.h b/platforms/chibios/drivers/i2c_master.h deleted file mode 100644 index 132ffd14c0..0000000000 --- a/platforms/chibios/drivers/i2c_master.h +++ /dev/null @@ -1,49 +0,0 @@ -/* Copyright 2018 Jack Humbert - * Copyright 2018 Yiancar - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -/* This library follows the convention of the AVR i2c_master library. - * As a result addresses are expected to be already shifted (addr << 1). - * I2CD1 is the default driver which corresponds to pins B6 and B7. This - * can be changed. - * Please ensure that HAL_USE_I2C is TRUE in the halconf.h file and that - * STM32_I2C_USE_I2C1 is TRUE in the mcuconf.h file. - */ -#pragma once - -#include <stdint.h> - -// ### DEPRECATED - DO NOT USE ### -#define i2c_writeReg(devaddr, regaddr, data, length, timeout) i2c_write_register(devaddr, regaddr, data, length, timeout) -#define i2c_writeReg16(devaddr, regaddr, data, length, timeout) i2c_write_register16(devaddr, regaddr, data, length, timeout) -#define i2c_readReg(devaddr, regaddr, data, length, timeout) i2c_read_register(devaddr, regaddr, data, length, timeout) -#define i2c_readReg16(devaddr, regaddr, data, length, timeout) i2c_read_register16(devaddr, regaddr, data, length, timeout) -// ############################### - -typedef int16_t i2c_status_t; - -#define I2C_STATUS_SUCCESS (0) -#define I2C_STATUS_ERROR (-1) -#define I2C_STATUS_TIMEOUT (-2) - -void i2c_init(void); -i2c_status_t i2c_transmit(uint8_t address, const uint8_t* data, uint16_t length, uint16_t timeout); -i2c_status_t i2c_receive(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout); -i2c_status_t i2c_write_register(uint8_t devaddr, uint8_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout); -i2c_status_t i2c_write_register16(uint8_t devaddr, uint16_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout); -i2c_status_t i2c_read_register(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout); -i2c_status_t i2c_read_register16(uint8_t devaddr, uint16_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout); -i2c_status_t i2c_ping_address(uint8_t address, uint16_t timeout); diff --git a/platforms/chibios/drivers/spi_master.c b/platforms/chibios/drivers/spi_master.c index 414e5b10a3..f5e48edfda 100644 --- a/platforms/chibios/drivers/spi_master.c +++ b/platforms/chibios/drivers/spi_master.c @@ -15,8 +15,49 @@ */ #include "spi_master.h" +#include "chibios_config.h" +#include <ch.h> +#include <hal.h> -#include "timer.h" +#ifndef SPI_DRIVER +# define SPI_DRIVER SPID2 +#endif + +#ifndef SPI_SCK_PIN +# define SPI_SCK_PIN B13 +#endif + +#ifndef SPI_SCK_PAL_MODE +# ifdef USE_GPIOV1 +# define SPI_SCK_PAL_MODE PAL_MODE_ALTERNATE_PUSHPULL +# else +# define SPI_SCK_PAL_MODE 5 +# endif +#endif + +#ifndef SPI_MOSI_PIN +# define SPI_MOSI_PIN B15 +#endif + +#ifndef SPI_MOSI_PAL_MODE +# ifdef USE_GPIOV1 +# define SPI_MOSI_PAL_MODE PAL_MODE_ALTERNATE_PUSHPULL +# else +# define SPI_MOSI_PAL_MODE 5 +# endif +#endif + +#ifndef SPI_MISO_PIN +# define SPI_MISO_PIN B14 +#endif + +#ifndef SPI_MISO_PAL_MODE +# ifdef USE_GPIOV1 +# define SPI_MISO_PAL_MODE PAL_MODE_ALTERNATE_PUSHPULL +# else +# define SPI_MISO_PAL_MODE 5 +# endif +#endif static bool spiStarted = false; #if SPI_SELECT_MODE == SPI_SELECT_MODE_NONE diff --git a/platforms/chibios/drivers/spi_master.h b/platforms/chibios/drivers/spi_master.h deleted file mode 100644 index 4ad6144091..0000000000 --- a/platforms/chibios/drivers/spi_master.h +++ /dev/null @@ -1,102 +0,0 @@ -/* Copyright 2020 Nick Brassel (tzarc) - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <https://www.gnu.org/licenses/>. - */ - -#pragma once - -#include <ch.h> -#include <hal.h> -#include <stdbool.h> - -#include "gpio.h" -#include "chibios_config.h" - -#ifndef SPI_DRIVER -# define SPI_DRIVER SPID2 -#endif - -#ifndef SPI_SCK_PIN -# define SPI_SCK_PIN B13 -#endif - -#ifndef SPI_SCK_PAL_MODE -# if defined(USE_GPIOV1) -# define SPI_SCK_PAL_MODE PAL_MODE_ALTERNATE_PUSHPULL -# else -# define SPI_SCK_PAL_MODE 5 -# endif -#endif - -#ifndef SPI_MOSI_PIN -# define SPI_MOSI_PIN B15 -#endif - -#ifndef SPI_MOSI_PAL_MODE -# if defined(USE_GPIOV1) -# define SPI_MOSI_PAL_MODE PAL_MODE_ALTERNATE_PUSHPULL -# else -# define SPI_MOSI_PAL_MODE 5 -# endif -#endif - -#ifndef SPI_MISO_PIN -# define SPI_MISO_PIN B14 -#endif - -#ifndef SPI_MISO_PAL_MODE -# if defined(USE_GPIOV1) -# define SPI_MISO_PAL_MODE PAL_MODE_ALTERNATE_PUSHPULL -# else -# define SPI_MISO_PAL_MODE 5 -# endif -#endif - -typedef int16_t spi_status_t; - -#define SPI_STATUS_SUCCESS (0) -#define SPI_STATUS_ERROR (-1) -#define SPI_STATUS_TIMEOUT (-2) - -#define SPI_TIMEOUT_IMMEDIATE (0) -#define SPI_TIMEOUT_INFINITE (0xFFFF) - -#ifdef __cplusplus -extern "C" { -#endif -typedef struct spi_start_config_t { - pin_t slave_pin; - bool lsb_first; - uint8_t mode; - uint16_t divisor; - bool cs_active_low; -} spi_start_config_t; - -void spi_init(void); - -bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor); -bool spi_start_extended(spi_start_config_t *start_config); - -spi_status_t spi_write(uint8_t data); - -spi_status_t spi_read(void); - -spi_status_t spi_transmit(const uint8_t *data, uint16_t length); - -spi_status_t spi_receive(uint8_t *data, uint16_t length); - -void spi_stop(void); -#ifdef __cplusplus -} -#endif diff --git a/platforms/chibios/drivers/uart.h b/platforms/chibios/drivers/uart.h deleted file mode 100644 index c1945575f1..0000000000 --- a/platforms/chibios/drivers/uart.h +++ /dev/null @@ -1,200 +0,0 @@ -// Copyright 2024 Stefan Kerkmann -// Copyright 2021 QMK -// Copyright 2024 Stefan Kerkmann -// SPDX-License-Identifier: GPL-2.0-or-later - -#pragma once - -#include <stdint.h> -#include <stdbool.h> - -#include <hal.h> - -#include "gpio.h" -#include "chibios_config.h" - -// ======== DEPRECATED DEFINES - DO NOT USE ======== -#ifdef SERIAL_DRIVER -# define UART_DRIVER SERIAL_DRIVER -#endif -#ifdef SD1_TX_PIN -# define UART_TX_PIN SD1_TX_PIN -#endif -#ifdef SD1_RX_PIN -# define UART_RX_PIN SD1_RX_PIN -#endif -#ifdef SD1_CTS_PIN -# define UART_CTS_PIN SD1_CTS_PIN -#endif -#ifdef SD1_RTS_PIN -# define UART_RTS_PIN SD1_RTS_PIN -#endif -#ifdef SD1_TX_PAL_MODE -# define UART_TX_PAL_MODE SD1_TX_PAL_MODE -#endif -#ifdef SD1_RX_PAL_MODE -# define UART_RX_PAL_MODE SD1_RX_PAL_MODE -#endif -#ifdef SD1_CTS_PAL_MODE -# define UART_RTS_PAL_MODE SD1_CTS_PAL_MODE -#endif -#ifdef SD1_RTS_PAL_MODE -# define UART_TX_PAL_MODE SD1_RTS_PAL_MODE -#endif -#ifdef SD1_CR1 -# define UART_CR1 SD1_CR1 -#endif -#ifdef SD1_CR2 -# define UART_CR2 SD1_CR2 -#endif -#ifdef SD1_CR3 -# define UART_CR3 SD1_CR3 -#endif -#ifdef SD1_WRDLEN -# define UART_WRDLEN SD1_WRDLEN -#endif -#ifdef SD1_STPBIT -# define UART_STPBIT SD1_STPBIT -#endif -#ifdef SD1_PARITY -# define UART_PARITY SD1_PARITY -#endif -#ifdef SD1_ATFLCT -# define UART_ATFLCT SD1_ATFLCT -#endif -// ======== - -#ifndef UART_DRIVER -# if (HAL_USE_SERIAL == TRUE) -# define UART_DRIVER SD1 -# elif (HAL_USE_SIO == TRUE) -# define UART_DRIVER SIOD1 -# endif -#endif - -#ifndef UART_TX_PIN -# define UART_TX_PIN A9 -#endif - -#ifndef UART_RX_PIN -# define UART_RX_PIN A10 -#endif - -#ifndef UART_CTS_PIN -# define UART_CTS_PIN A11 -#endif - -#ifndef UART_RTS_PIN -# define UART_RTS_PIN A12 -#endif - -#ifdef USE_GPIOV1 -# ifndef UART_TX_PAL_MODE -# define UART_TX_PAL_MODE PAL_MODE_ALTERNATE_PUSHPULL -# endif -# ifndef UART_RX_PAL_MODE -# define UART_RX_PAL_MODE PAL_MODE_INPUT -# endif -# ifndef UART_CTS_PAL_MODE -# define UART_CTS_PAL_MODE PAL_MODE_INPUT -# endif -# ifndef UART_RTS_PAL_MODE -# define UART_RTS_PAL_MODE PAL_MODE_ALTERNATE_PUSHPULL -# endif -#else -# ifndef UART_TX_PAL_MODE -# define UART_TX_PAL_MODE 7 -# endif - -# ifndef UART_RX_PAL_MODE -# define UART_RX_PAL_MODE 7 -# endif - -# ifndef UART_CTS_PAL_MODE -# define UART_CTS_PAL_MODE 7 -# endif - -# ifndef UART_RTS_PAL_MODE -# define UART_RTS_PAL_MODE 7 -# endif -#endif - -#ifndef UART_CR1 -# define UART_CR1 0 -#endif - -#ifndef UART_CR2 -# define UART_CR2 0 -#endif - -#ifndef UART_CR3 -# define UART_CR3 0 -#endif - -#ifndef UART_WRDLEN -# define UART_WRDLEN 3 -#endif - -#ifndef UART_STPBIT -# define UART_STPBIT 0 -#endif - -#ifndef UART_PARITY -# define UART_PARITY 0 -#endif - -#ifndef UART_ATFLCT -# define UART_ATFLCT 0 -#endif - -/** - * @brief Initialize the UART driver. This function must be called only once, - * before any of the below functions can be called. - * - * @param baud The baud rate to transmit and receive at. This may depend on the - * device you are communicating with. Common values are 1200, 2400, 4800, 9600, - * 19200, 38400, 57600, and 115200. - */ -void uart_init(uint32_t baud); - -/** - * @brief Transmit a single byte. - * - * @param data The byte to transmit. - */ -void uart_write(uint8_t data); - -/** - * @brief Receive a single byte. - * - * @return uint8_t The byte read from the receive buffer. This function will - * block if the buffer is empty (ie. no data to read). - */ -uint8_t uart_read(void); - -/** - * @brief Transmit multiple bytes. - * - * @param data A pointer to the data to write from. - * @param length The number of bytes to write. Take care not to overrun the - * length of `data`. - */ -void uart_transmit(const uint8_t *data, uint16_t length); - -/** - * @brief Receive multiple bytes. - * - * @param data A pointer to the buffer to read into. - * @param length The number of bytes to read. Take care not to overrun the - * length of `data`. - */ -void uart_receive(uint8_t *data, uint16_t length); - -/** - * @brief Return whether the receive buffer contains data. Call this function - * to determine if `uart_read()` will return data immediately. - * - * @return true If there is data available to read. - * @return false If there is no data available to read. - */ -bool uart_available(void); diff --git a/platforms/chibios/drivers/uart_serial.c b/platforms/chibios/drivers/uart_serial.c index 6aff4eae47..e0afb9768a 100644 --- a/platforms/chibios/drivers/uart_serial.c +++ b/platforms/chibios/drivers/uart_serial.c @@ -3,6 +3,89 @@ // SPDX-License-Identifier: GPL-2.0-or-later #include "uart.h" +#include "gpio.h" +#include "chibios_config.h" +#include <hal.h> + +#ifndef UART_DRIVER +# define UART_DRIVER SD1 +#endif + +#ifndef UART_TX_PIN +# define UART_TX_PIN A9 +#endif + +#ifndef UART_TX_PAL_MODE +# ifdef USE_GPIOV1 +# define UART_TX_PAL_MODE PAL_MODE_ALTERNATE_PUSHPULL +# else +# define UART_TX_PAL_MODE 7 +# endif +#endif + +#ifndef UART_RX_PIN +# define UART_RX_PIN A10 +#endif + +#ifndef UART_RX_PAL_MODE +# ifdef USE_GPIOV1 +# define UART_RX_PAL_MODE PAL_MODE_INPUT +# else +# define UART_RX_PAL_MODE 7 +# endif +#endif + +#ifndef UART_CTS_PIN +# define UART_CTS_PIN A11 +#endif + +#ifndef UART_CTS_PAL_MODE +# ifdef USE_GPIOV1 +# define UART_CTS_PAL_MODE PAL_MODE_INPUT +# else +# define UART_CTS_PAL_MODE 7 +# endif +#endif + +#ifndef UART_RTS_PIN +# define UART_RTS_PIN A12 +#endif + +#ifndef UART_RTS_PAL_MODE +# ifdef USE_GPIOV1 +# define UART_RTS_PAL_MODE PAL_MODE_ALTERNATE_PUSHPULL +# else +# define UART_RTS_PAL_MODE 7 +# endif +#endif + +#ifndef UART_CR1 +# define UART_CR1 0 +#endif + +#ifndef UART_CR2 +# define UART_CR2 0 +#endif + +#ifndef UART_CR3 +# define UART_CR3 0 +#endif + +#ifndef UART_WRDLEN +# define UART_WRDLEN 3 +#endif + +#ifndef UART_STPBIT +# define UART_STPBIT 0 +#endif + +#ifndef UART_PARITY +# define UART_PARITY 0 +#endif + +#ifndef UART_ATFLCT +# define UART_ATFLCT 0 +#endif #if defined(MCU_KINETIS) static SerialConfig serialConfig = {SERIAL_DEFAULT_BITRATE}; diff --git a/platforms/chibios/drivers/uart_sio.c b/platforms/chibios/drivers/uart_sio.c index 442df1c54d..fc12f0abed 100644 --- a/platforms/chibios/drivers/uart_sio.c +++ b/platforms/chibios/drivers/uart_sio.c @@ -3,6 +3,73 @@ // SPDX-License-Identifier: GPL-2.0-or-later #include "uart.h" +#include "gpio.h" +#include "chibios_config.h" +#include <hal.h> + +#ifndef UART_DRIVER +# define UART_DRIVER SIOD1 +#endif + +#ifndef UART_TX_PIN +# define UART_TX_PIN A9 +#endif + +#ifndef UART_TX_PAL_MODE +# ifdef USE_GPIOV1 +# define UART_TX_PAL_MODE PAL_MODE_ALTERNATE_PUSHPULL +# else +# define UART_TX_PAL_MODE 7 +# endif +#endif + +#ifndef UART_RX_PIN +# define UART_RX_PIN A10 +#endif + +#ifndef UART_RX_PAL_MODE +# ifdef USE_GPIOV1 +# define UART_RX_PAL_MODE PAL_MODE_INPUT +# else +# define UART_RX_PAL_MODE 7 +# endif +#endif + +#ifndef UART_CTS_PIN +# define UART_CTS_PIN A11 +#endif + +#ifndef UART_CTS_PAL_MODE +# ifdef USE_GPIOV1 +# define UART_CTS_PAL_MODE PAL_MODE_INPUT +# else +# define UART_CTS_PAL_MODE 7 +# endif +#endif + +#ifndef UART_RTS_PIN +# define UART_RTS_PIN A12 +#endif + +#ifndef UART_RTS_PAL_MODE +# ifdef USE_GPIOV1 +# define UART_RTS_PAL_MODE PAL_MODE_ALTERNATE_PUSHPULL +# else +# define UART_RTS_PAL_MODE 7 +# endif +#endif + +#ifndef UART_CR1 +# define UART_CR1 0 +#endif + +#ifndef UART_CR2 +# define UART_CR2 0 +#endif + +#ifndef UART_CR3 +# define UART_CR3 0 +#endif #if defined(MCU_RP) // 38400 baud, 8 data bits, 1 stop bit, no parity, no flow control diff --git a/platforms/chibios/drivers/usbpd_stm32g4.c b/platforms/chibios/drivers/usbpd_stm32g4.c index 21b8f6db95..7603b5627b 100644 --- a/platforms/chibios/drivers/usbpd_stm32g4.c +++ b/platforms/chibios/drivers/usbpd_stm32g4.c @@ -76,4 +76,4 @@ __attribute__((weak)) usbpd_allowance_t usbpd_get_allowance(void) { } return USBPD_500MA; -}
\ No newline at end of file +} diff --git a/platforms/chibios/drivers/wear_leveling/wear_leveling_efl.c b/platforms/chibios/drivers/wear_leveling/wear_leveling_efl.c index fed16d20b1..fec4646a5b 100644 --- a/platforms/chibios/drivers/wear_leveling/wear_leveling_efl.c +++ b/platforms/chibios/drivers/wear_leveling/wear_leveling_efl.c @@ -4,6 +4,7 @@ #include <hal.h> #include "timer.h" #include "wear_leveling.h" +#include "wear_leveling_efl_config.h" #include "wear_leveling_internal.h" static flash_offset_t base_offset = UINT32_MAX; diff --git a/platforms/chibios/drivers/wear_leveling/wear_leveling_legacy.c b/platforms/chibios/drivers/wear_leveling/wear_leveling_legacy.c index 7c6fd2d808..3d2af625ca 100644 --- a/platforms/chibios/drivers/wear_leveling/wear_leveling_legacy.c +++ b/platforms/chibios/drivers/wear_leveling/wear_leveling_legacy.c @@ -4,6 +4,7 @@ #include <hal.h> #include "timer.h" #include "wear_leveling.h" +#include "wear_leveling_legacy_config.h" #include "wear_leveling_internal.h" #include "legacy_flash_ops.h" diff --git a/platforms/chibios/drivers/wear_leveling/wear_leveling_rp2040_flash.c b/platforms/chibios/drivers/wear_leveling/wear_leveling_rp2040_flash.c index 6624c30b5b..2f3c7c58ca 100644 --- a/platforms/chibios/drivers/wear_leveling/wear_leveling_rp2040_flash.c +++ b/platforms/chibios/drivers/wear_leveling/wear_leveling_rp2040_flash.c @@ -6,15 +6,18 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include <stdbool.h> + #include "pico/bootrom.h" #include "hardware/flash.h" #include "hardware/sync.h" #include "hardware/structs/ssi.h" #include "hardware/structs/ioqspi.h" -#include <stdbool.h> +#include "compiler_support.h" #include "timer.h" #include "wear_leveling.h" +#include "wear_leveling_rp2040_flash_config.h" #include "wear_leveling_internal.h" #ifndef WEAR_LEVELING_RP2040_FLASH_BULK_COUNT @@ -177,7 +180,7 @@ bool backing_store_erase(void) { #endif // Ensure the backing size can be cleanly subtracted from the flash size without alignment issues. - _Static_assert((WEAR_LEVELING_BACKING_SIZE) % (FLASH_SECTOR_SIZE) == 0, "Backing size must be a multiple of FLASH_SECTOR_SIZE"); + STATIC_ASSERT((WEAR_LEVELING_BACKING_SIZE) % (FLASH_SECTOR_SIZE) == 0, "Backing size must be a multiple of FLASH_SECTOR_SIZE"); interrupts = save_and_disable_interrupts(); flash_range_erase((WEAR_LEVELING_RP2040_FLASH_BASE), (WEAR_LEVELING_BACKING_SIZE)); |